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Table of Contents
Summary of Contents for Terasic ALTERA HSMC-DVI
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Page 2: Table Of Contents
CONTENTS Chapter 1 Introduction of the HSMC-DVI ....................2 1.1 Features................................ 2 1.2 About the KIT .............................. 3 1.3 Assemble the HSMC-DVI Board ........................ 4 Chapter 2 HSMC-DVI Card Architecture ....................7 2.1 Layout and Components ..........................7 2.2 Block Diagram of the DVI Board ........................ 9 Chapter 3 Board Components ...................... -
Page 3: Introduction Of The Hsmc-Dvi
Chapter 1 Introduction of the HSMC-DVI The Terasic HSMC-DVI is a DVI transmitter/receiver board with a High Speed Mezzanine Connector (HSMC) interface. It is designed to allow developers to access high quality and high resolution video signals in their FPGA. It gives the flexibility required in high resolution image processing systems by combining both the DVI transmitter and receiver onto the same card. -
Page 4: About The Kit
One DVI receiver with single receiving port Supports UXGA Resolution (Output Pixel Rates Up to 165 MHz) Digital Visual Interface (DVI) Specification Compliant True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock Laser Trimmed Internal termination Resistors for Optimum Fixed Impedance Matching ... -
Page 5: Assemble The Hsmc-Dvi Board
The CD contains technical documents of the HSMC-DVI, and one reference design along with the source code. The source code of reference design are available for the following FPGA main board: A5SK: Arria V Starter Kit S5GFP: Stratix V GX FPGA Programmable Board ... - Page 6 Figure 1-3 The HSMC-DVI board connects with S5GFP Figure 1-4 The HSMC-DVI board connects with C5EFP...
- Page 7 Note. Do not attempt to connect/remove the HSMC-DVI daughter board to/from the main the main board when the power is on, or else the hardware could be damaged. Here are some places to get help if you encounter any problem: • Email to support@terasic.com • Taiwan & China: +886-3-575-0880 • Korea : +82-2-512-7661...
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Page 8: Hsmc-Dvi Card Architecture
Chapter 2 HSMC-DVI Card Architecture This Chapter covers the architecture of the HSMC-DVI board including its PCB and block diagram. The picture of the HSMC-DVI board is shown in Figure 2-2 It depicts the layout of Figure 2-1 the board and indicates the location of the connectors and key components. Figure 2-1 The HSMC-DVI PCB and component diagram... - Page 9 Figure 2-2 The HSMC-DVI Back side – HSMC connector vie The following components are provided on the HSMC-DVI board : • DVI Transmitter (U2) • DVI Receiver (U3) • I2C EEPROM (U4) • DVI Transmitter Connector (J2) • DVI Receiver Connector (J3) •...
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Page 10: Block Diagram Of The Dvi Board
Figure 2-3 The block diagram of the HSMC-DVI board... -
Page 11: Chapter 3 Board Components
Chapter 3 Board Components This section illustrates the detailed information of the components, connector interfaces, and the pin mapping tables of the HSMC-DVI board. This section describes pin definition of the HSMC-DVI interface onboard. All the control and data signals of the DVI transmitter and receiver are connected to the HSMC connector, so users can fully control the HSMC-DVI daughter board through the HSMC interface. - Page 12 Figure 3-1 The pin-outs on the HSMC connecotor...
- Page 13 Table 3-1 below lists the HSMC signal direction and description. Note. The power pins are not shown in the table Table 3-1 Pin Numbers Name Direction Description N.C. Not Connect N.C. Not Connect N.C. Not Connect N.C. Not Connect N.C. Not Connect N.C.
- Page 14 N.C. Not Connect DVI_RX_D0 Input DVI receiver pixel data DVI_RX_D14 Input DVI receiver pixel data DVI_RX_D1 Input DVI receiver pixel data DVI_RX_D15 Input DVI receiver pixel data Power Power 3.3V Power Power 12V DVI_RX_D2 Input DVI receiver pixel data DVI_RX_D13 Input DVI receiver pixel data DVI_RX_D3...
- Page 15 DVI_RX_DDCS Inout DDC I² C data DVI_RX_D1 Input DVI receiver pixel data DVI_RX_DDSC Inout DDC I² C clock DVI_RX_D0 Input DVI receiver pixel data Power Power 3.3V Power Power 12V EDID_WP_n Output I² C write protect enable DVI_RX_SCDT Input Receiver sync detect N.C.
- Page 16 Power Power 3.3V Power Power 12V DVI_TX_D7 Output DVI transmitter data bus DVI_TX_VS Output DVI transmitter vertical sync DVI_TX_D6 Output DVI transmitter data bus DVI_TX_CTL3 Output Multifunction Power Power 3.3V Power Power 12V DVI_TX_D5 Output DVI transmitter data bus DVI_TX_CTL2 Output Multifunction DVI_TX_D4...
- Page 17 Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground Power Power Ground...
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Page 18: Chapter 4 Demonstrations
Chapter 4 Demonstrations This Chapter illustrates the reference design for the HSMC-DVI board. This section describes the functionality of the demonstration briefly. The demonstration shows how to use Altera’s 28nm-FPGA development kits to interface with the HSMC-DVI board, which include: •... -
Page 19: System Requirements
Loopback the DVI video signals within the FPGA board (internal bypass). The video output pins of the receiver are directly connected to the input video pins of the transmitter. The following items are required for the HSMC-DVI Server demonstration. • HSMC-DVI Daughter Card x 1 •... -
Page 20: Demo Operation
Configure the FPGA by programming the bit stream file: DVI_Demo.sof The bit stream file is located in the project directory as shown below: • Stratix V GX FPGA Development Kit: S5GFP_DVI • Arria V GX Starter Kit: A5SK_DVI • Cyclone V GX FPGA Development Kit: C5GFP_DVI •... - Page 21 Figure 4-2 Block diagram The “Video Pattern Generator” module corresponds to the generated test patterns for transmission demo. The test patterns include: Pattern ID Video Format PCLK (MHZ)
- Page 22 640x480@60P 720x480@60P 1024x768@60P 3 1280x1024@60P 4 1920x1080@60P 148.5 5 1600x1200@60P The display resolution and pixel rate will change when the mode changes. In this module, the Altera IP “PLL Reconfig” is used to set various pixel rates to the Altera IP “PLL”. The RECONFIG data for various clocks are from “PLL Controller”.
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Page 23: Chapter 5 Appendix
Modify function block Nov 22, 2017 Modify the Universal Graphics Controller Interface description Copyright © 2015 Terasic Technologies. All rights reserved. We will be continuing providing interesting examples and labs on our HSMC-DVI webpage. Please visit www.altera.com or dvi.terasic.com for more information.