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Page 2 PLC 2/30 Programmable Controller Programming and Operations Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 3 In no event will Allen-Bradley Company, Inc. be responsible or liable for indirect or consequential damages resulting from the use or application of this equipment.
Page 4 Table of Contents Introduction ........Hardware Considerations .
Page 5: Introduction 1
Table of Contents Introduction to Programming ..... . . Timer and Counter Instructions ..... Artisan Technology Group - Quality Instrumentation ...
Page 6 Table of Contents Data Manipulation Instructions ..... Output Override and I/O Update Instructions ... Artisan Technology Group - Quality Instrumentation ...
Page 7 Table of Contents Peripheral Functions ......Report Generation ....... Block Transfer .
Page 8 Table of Contents Jump Instructions and Subroutine Programming ..11 1 Data Transfer File Instructions ..... . 12 1 Artisan Technology Group - Quality Instrumentation ...
Page 9 Table of Contents Shift Register Instructions ......13 1 Bit Shifts ........14 1 Sequencer Instructions .
Page 10 Table of Contents File Logic Instructions ......16 1 File Search and File Diagnostic Instructions .
Page 11 viii Table of Contents Number Systems ....... . Programming .01 Second Timers .
Page 12 - extended arithmetic functions - relay-type functions - and data transfer, for a few examples. This manual is your entry into understanding the PLC-2/30 programmable controller. To find what the topics are in the individual chapters — Use the Table of Contents.
Page 13 Chapter 1 Introduction With a user-written program and appropriate I/O modules, the PLC-2/30 programmable controller can be used to control many types of industrial applications such as: Process control Material handling Palletizing Measurement and gauging Pollution control and monitoring The 1772-LP3 processor has a read/write CMOS memory that stores user program instructions, numeric values and I/O device status.
Page 14 Chapter 1 Introduction Functional Block Instructions - Shift Register instructions - File-to-File and Word-to-File Logic instructions - File-to-File, Word-to-File and File-to-Word transfer instructions Binary to BCD and BCD to Binary conversions On-line programming Data Highway and Data Highway II compatible Sequencers Contact histogram Report generation...
Page 15 Remote I/O Scanner/Distribution Panel Product Data (publication 1772-2.18). 1.2.2 With the proper interface module, the PLC-2/30 processor can be connected to the Allen-Bradley Data Highway or other industry standard Data Highway Compatibility buses. Table 1.B lists several “from-to” possibilities and the Allen-Bradley module used to accomplish that function.
Page 16 WARNING: Do not use a 1770-T1 or 1770-T2 industrial terminal to edit or change a program or data table values in PLC-2/30 memory that were generated using a 1770-T3 industrial terminal. Block instructions and instructions with word addresses 4008 or greater will not be displayed properly (Figure 1.1).
Page 17 Chapter 1 Introduction We use the following terms to describe the various parts of your PLC-2/30 system. Terms Used in This Manual Chassis — a hardware assembly used to house PC devices such as I/O modules, adapter modules, processor modules, power supplies and some processors (PLC-2/02, -2/16 and -2/17, for example).
Page 18: Hardware Considerations 2
This chapter describes only those hardware items required when programming or operating the PLC-2/30 programmable controller. For General more complete hardware information, refer to the PLC-2/20, PLC-2/30 Programmable Controller Assembly and Installation Manual (publication no. 1772-6.6.2). A four-position mode select switch (Figure 2.1) is located on the front of the processor.
Page 19 Chapter 2 Hardware Considerations Figure 2.1 PLC 2/30 Processor Diagnostic Keylock Mode Indicators Select Switch When the memory write protect jumper (Figure 2.2) is removed from a 1772-LH processor interface module, data table values can be changed Memory Write Protect between word addresses 010 and 377 .
Page 20 Chapter 2 Hardware Considerations Figure 2.2 Memory Write Protect Jumper HALFTONE WITH CALLOUT The remaining words in memory from 400 to the end of memory, including data table and user program, are protected and cannot be altered by programming. The memory write protect feature guards against unintentional changes to processor memory.
Page 21 Chapter 2 Hardware Considerations modes, program or remote program. (If the keyswitch is in RUN/PROGRAM position, the industrial terminal automatically puts the processor into remote program mode. If the keyswitch is in the RUN position, or when it is connected to the processor through the 1771-KA2 communications adapter module, you must manually change the keyswitch to the PROGRAM position).
Page 22 The switch and its functions, when used in local racks, are shown in Figure 2.3. In this setup, the PLC-2/30 is communicating with the I/O chassis through a 1771-AL Local I/O Adapter module. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 23 Chapter 2 Hardware Considerations When using remote I/O (the 1772-SD2 scanner and the 1771-ASB remote I/O Adapter), these switches will be set according to the adapter module’s requirements. 2.6.1 The last state switch (switch no. 1) on the 1771 I/O chassis must be properly set.
Page 24 Up to 7 local I/O racks may be assigned. Local System Structure For proper transmission of data between the PLC-2/30 processor and local bulletin 1771 I/O modules, the I/O chassis must contain a local I/O Adapter Module (Cat. No. 1771-AL). The local adapter module must be installed in each I/O chassis used with the processor.
Page 25 Missing terminator plug Disconnected/broken communications cable No power at the processor. An I/O Interconnect cable is required to connect between the PLC-2/30 and local I/O rack adapter modules. It is available in two sizes: 3 ft. I/O Interconnect cable (.92m) 1777–CA...
Page 26 Local/Remote System assigned. Structure The PLC-2/30 processor system can also be configured with a combination of local and remote I/O chassis. Each local chassis must have a 1771-AL Local I/O Adapter module. And as previously stated, communication with the remote chassis (one or more) requires a 1772-SD2 Remote Distribution panel and one 1771-ASB Remote I/O Adapter in each chassis.
Page 27 Chapter 2 Hardware Considerations CAUTION: For proper system data communications, a local/remote system structure with 2 local racks, you must use a 1777-CA cable (3 ft./.92m) between the processor and the two local racks. You must also use the 1772-CS cable (3 ft./.92m) from the second local rack to the distribution panel.
Page 28 The power supply must be used to power the Supply 1772-SD2 distribution panel when the PLC-2/30 processor contains a core memory module. This power supply may be operated from either a 120 or a 220/240V AC source.
Page 29 It explains the General memory organization of the PLC-2/30 programmable controller. The memory of the processor can be thought of as a large arrangement of storage points, each called a BInary digiT, or bit (Figure 3.1). A bit is the Memory Structure smallest unit of information a memory is capable of retaining.
Page 30 A group of 16 bits makes up a word. This word can be thought of as being made up of two 8-bit bytes; a lower byte and an upper byte. Because of its function in memory, one PLC-2/30 word may also be thought of as a memory location: when a word is being used, an actual physical location in memory is being accessed.
Page 31 Chapter 3 Figure 3.2 PLC 2/30 Memory Organization (Expanded Data Table) Output Image Table Input Image Table status Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 32 Data Table Areas The data table of the PLC-2/30 programmable controller can be divided into six distinct areas, assuming default data table size has not been changed (Figure 3.3). These areas are:...
Page 33 Actual hardware outputs change state only if corresponding output image table bits change state or if they are forced. NOTE: PLC-2/30 output terminals can be forced on or off through the industrial terminal. The output image table bits, corresponding to output terminals which are forced, do not change state.
Page 34 1771-A4B I/O chassis), the 896 bit addresses represent the maximum number of discrete inputs the processor can monitor. In a local PLC-2/30 controller, the total bits used, which represent actual hardware inputs and outputs together, cannot exceed 896 I/O. This number...
Page 35 Chapter 3 CAUTION: If a remote I/O configuration is being used, words 1258 and 1268 may be used to store remote I/O fault bits. If this is the case, input modules must not be placed in these slots (rack 2, I/O groups 5 and 6): unexpected machine operation may result.
Page 36 Chapter 3 Figure 3.3 PLC 2/30 Memory Organization (Default Configuration) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 37 Chapter 3 Each bit in the input image table may have a corresponding real hardware terminal on the I/O rack associated with it, although this may not always be the case, since a corresponding input module may not actually be placed in an I/O rack slot.
Page 38 Chapter 3 Figure 3.4 Relation of Word Address to Hardware Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 39 Chapter 3 Timer/Counter Preset Values, Bit/Word Storage This area of memory is used to store preset values of timer/counter instructions. The area may also be used as storage for words and/or bits. Word addresses 130 to 177 bound this area when memory is configured for 256 I/O (maximum) and 40 Timer/Counter Instructions (Figure 3.3).
Page 40 Chapter 3 Table 3.A Data Table Configuration Function Mode Key Sequence Description Data Table Area Configuration The data table is factory-configured for 128 words (Figure 3.2). The data table size can be decreased to 48 words or expanded to 8,064 words (with 8K memory) or 8,192 words (with 16K memory).
Page 41 Chapter 3 After you have determined the layout of the data table, press [SEARCH] [5] [0]. The following display appears: NUMBER OF 128-WORD DATA TABLE SECTIONS NUMBER OF I/O RACKS NUMBER OF TIMERS/COUNTERS (IF APPLICABLE) DATA TABLE SIZE The number of 128-word data table sections, the number of I/O racks (1-7), and the number of timers/counters (if applicable) to be entered is prompted by a reverse-video cursor.
Page 42 Chapter 3 After the number of I/O racks is selected, the industrial terminal will compute and enter the data table size. Anytime you reduce the size of the data table, the processor searches for instructions in those areas. If an instruction exists in an area to be deleted, the change will not be allowed and the following message will be displayed: “INSTRUCTION EXISTS IN DELETED AREA.”...
Page 43 Chapter 3 additional 7 timer/counter instructions become available. The previous output image table addresses 020 -026 are now reserved for timer/counter accumulated values; previous input image table addresses 120 -126 , for timer/counter preset values. When I/O requirements are increased from the standard value of 256 to 384 (or from 2 racks to 3 racks), data table size does not change.
Page 44 Chapter 3 3.2.2 You program is a group of ladder diagram instructions used to control an application. It is initially entered into memory using an industrial terminal. User Program Main Program The main program follows the data table in memory and stores all the user program instructions that make up the ladder diagram program.
Page 45: Report Generation 9
Chapter 3 3.2.3 The message storage area begins after the END of user program statement and it stores the alphanumeric characters of the messages. Message Storage Area The memory is capable of storing user-programmed messages for hardcopy printout by compatible RS-232C data terminals. As many as 70 messages of varying length can be stored (198 messages can be stored when using the 1770-RG Report Generation module).
Page 46 Chapter 3 If a bit is off (0), its corresponding output device is off (de-energized). Output image table bits are controlled by user program instructions. 3.3.2 Instruction addresses in the input/output (I/O) image tables take the form of Figure 3.5. These addresses have a dual role. Each 5-digit address Instruction Address corresponds (1) to an input or output table word (address) and (2) to a hardware location.
Page 47 Chapter 3 Figure 3.5 Instruction Address Terminology Concept Example Hardware Terminology Hardware Terminology Data Table Terminology Instruction Address Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 48 Chapter 3 Figure 3.6 Bit Address to Hardware Relationship (2 slot Addressing) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 49 Chapter 3 3.3.3 The hardware-program interface is illustrated in Figure 3.7 by showing the operational relationship between the input and output devices, the Fundamental Operation input/output image table and the user program. When an input device connected to terminal 113/12 is closed, the input module circuitry senses a voltage.
Page 50 Chapter 3 Figure 3.7 Relationship of Word Address to Hardware When the input device wired to terminal 113/12 opens, the input module senses no voltage. The Off condition is reflected in the input image table bit 113/12. During the program scan, the processor examines bit 113/12 for an On (1) condition.
Page 51 Chapter 3 As you program your application, you should carefully record the data table addresses of the program elements. The importance of this Data Table Documentation documentation cannot be overemphasized. You will find it invaluable for Forms avoiding improper use of data table areas and as an aid in troubleshooting and making program changes.
Page 52 Chapter 3 Figure 3.8 Example of Data Table Word Map Out- Storage Storage Block Xfer puts Timer/Counter AC Values Storage Inputs Storage Block Xfer Used Timer/Counter PR Values Storage Files 3.4.2 This form can be used to log the bit status of a word and to describe the function of groups of related words within a 128–word data table section.
Page 53 Chapter 3 Figure 3.9 Example of Data Table Map 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 FFM 062 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 (Binary) 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0...
Page 54 Chapter 3 Figure 3.10 Example of Data Table Word Assignments Master cycle time, AC Master cycle time, PR Drillhead #1, dwell time, AC Drillhead #1, dwell time, PR No. of passes, AC No. of passes, PR No. of reject parts, AC No.
Page 55 Chapter 3 3.4.5 This form can be used for any one of the three Sequencer instructions to log the data associated with each step. Sequencer Table Bit Assignments This information added to the heading of the assignment sheet should be identical to the information displayed in the data monitor mode heading and in the ladder diagram mode instruction block of the sequencer instruction.
Page 56 The installer and programmer of the PLC-2/30 Programmable Controller should work together to determine the best placement of the I/O modules within the I/O chassis. To simplify installation and troubleshooting procedures, it may be desirable to group like modules together.
Page 57 The first available timer/counter address depends on the number of I/O racks used. The PLC-2/30 Processor (Cat. No. 1772-LP3) can have up to 7 I/O racks. The corresponding addresses for the first timer/counter locations are shown in Table 3.B.
Page 58 Chapter 3 Output image table words can be used for storage when the corresponding input image table words are used for nonblock transfer input modules. However, when there is a vacant I/O group or slot in the I/O chassis, do not use image table words for storage. This will allow room for future system expansion.
Page 59 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 60 Bulletin 1771 I/O Chassis CONNECTION DIAGRAM ADDRESSING WORKSHEET (16-point Modules) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 61 Chapter 3 ALLEN-BRADLEY Programmable Controller DATA TABLE WORD MAP (1024 WORD) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 62 Chapter 3 ALLEN-BRADLEY Programmable Controller DATA TABLE WORD MAP (128 WORD) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 63 Chapter 3 ALLEN-BRADLEY Programmable Controller DATA TABLE WORD ASSIGNMENTS (64 WORD) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 64 Chapter 3 ALLEN-BRADLEY Programmable Controller DATA TABLE BIT ASSIGNMENTS Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 65 Chapter 3 ALLEN-BRADLEY Programmable Controller SEQUENCER TABLE BIT ASSIGNMENTS Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 66 Assuming that the data table size has not been changed from factory-configured values, the user program begins after word address In certain applications, this area of PLC-2/30 memory can further be divided into data highway instructions, main ladder diagram program and subroutine area.
Page 67 Chapter 4 Programmable controller ladder diagram logic closely resembles hardwired relay logic. Hardwired relay control systems require electrical continuity Ladder Diagram Logic to turn output devices on and off. For example, the relay diagram in Figure 4.1 shows that limit switch LS1 and relay contact CR2 must be closed to energize relay coil CR4.
Page 68 Chapter 4 Programmable controllers have many of the capabilities of hardwired relay control systems. Control functions similar to those available with relays are Relay Type Instructions provided by the following relay-type instructions: Examine instructions Output instructions Branch instructions 4.3.1 There are two examine instructions: Examine Instructions Examine On –| |–...
Page 69 Chapter 4 The condition of the Examine On instruction is either true or false: True – the addressed memory bit is one, meaning that the corresponding I/O device or bit is on False – The addressed memory bit is zero, meaning that the corresponding I/O device or bit is off When using the Examine On instruction to address an input device, the conventional normally open or normally closed distinctions are not made.
Page 70 Chapter 4 Figure 4.5 Examine Off Instruction 4.3.2 The output instructions set an addressed memory bit to one (on) or reset it to zero (off). An output image table bit, as one or zero, can cause an output Output Instructions device to be turned on or off.
Page 71 Chapter 4 CAUTION: The Output Energize instruction can be programmed unconditionally for some types of specialized programming. Its use should be limited to storage bits for these special purposes. An unconditional output energize instruction (Figure 4.7) causes the output instruction to remain energized continuously.
Page 72 Chapter 4 by an Output Unlatch instruction. If power is lost and back-up battery for CMOS RAM memory is maintained, all latched bits will remain on. The Output Unlatch instruction is used to de-energize a memory bit that has been latched on. The Output Unlatch instruction addresses the same memory bit that has been latched on (Figure 4.8).
Page 73 Chapter 4 When the Mode Select Switch is changed from the RUN or RUN/PROG position, the last true Output Latch or Output Unlatch instruction continues to control the addressed memory bit, but disables the output device. When the Mode Select Switch is turned back to RUN or RUN/PROG position, a latched output device will be energized.
Page 74 Chapter 4 4.3.3 The branch instructions allow more than one combination of input conditions to energize an output device (Figure 4.11). Branch Instructions These are two branch instructions: Branch Start Branch End Figure 4.11 Branching Instructions Branch Start This instruction begins each parallel logic branch of a rung. The Branch Start is programmed immediately before the first instruction of each parallel logic path.
Page 75 Chapter 4 Figure 4.12 Nested Branching vs. Equivalent Logic WARNING: While inserting a BRANCH START instruction to an existing rung during on-line programming, the actual output status (ON or OFF) may not be the logically expected state of the rung. This condition exists until the BRANCH END instruction is installed and the rung is completed.
Page 76 Chapter 4 Figure 4.13 Example Original Rung With First Part of Duplicate Rung Cursor to the point where you want to change the logic and insert the BRANCH START. Insert the desired parallel logic (see Figure 4.14). Insert the BRANCH END. Figure 4.14 Example New Rung With Branch Instruction Now insert the output instruction.
Page 77 Additional program instructions cannot be entered. Most PLC-2/30 instructions take an average of 3 to 6 msec for the processor to scan and execute. The execution time for different instructions varies considerably and is dependent on the exact instruction and its true/false state.
Page 78 Using unauthorized programming devices may result in unexpected operation, possibly causing equipment damage and/or injury to personnel. The Allen-Bradley Company will not be responsible or liable for any damages, whether direct, indirect, or consequential, arising out of the use of such unauthorized programming devices.
Page 79 Chapter 4 Table 4.A Relay Type Instructions NOTE: Keytop Symbol Instruction Name 1770 T3 Display Description This section contains the operating instructions that are used to move through the program and perform a variety of functions. Operating Instructions Addressing Help directories Searching Editing On-line programming...
Page 80 [SEARCH] or [FILE] key. A master help directory is also available which lists the eight function and instruction directories for the PLC-2/30 and the key sequence to access them. The master help directory is displayed by pressing the [HELP] key.
Page 81 Chapter 4 Table 4.B Help Directories Function Mode Key Sequence Description 4.4.3 The industrial terminal can be used to search the user program for: Searching Specific instruction and specific word addresses First or last instruction in a rung Single rung display Incomplete rung First and last rung and user boundaries Remote Mode Select...
Page 82 Chapter 4 entered is the word address for the Output instructions. The industrial terminal will locate all uses of the word addresses associated with the word address except for –| |– and–|/|–. Table 4.C SEARCH Functions Function Mode Key Sequence Description Once either key sequence is pressed, this information and an EXECUTING SEARCH message will be displayed near the bottom of the screen.
Page 83 Chapter 4 If found, the rung containing the first occurrence of the address and/or instruction will be displayed as well as the rungs after it. If the SEARCH key is pressed again, the next occurrence of the address and/or instruction will be displayed.
Page 84 Chapter 4 The cursor will go directly to the first rung from anywhere in user program by pressing the [SEARCH][ ] keys. When the [SEARCH][ ] key sequence is pressed, the display will go to the next boundary in the first section indicated. By pressing the [SEARCH][ ] key sequence again, a subsequent boundary will be displayed until the user program end statement is reached.
Page 85 Chapter 4 Table 4.D Editing Functions Function Mode Key Sequence Description NOTE: Inserting an Instruction Only nonoutput instructions can be inserted in a rung. There are two ways of doing this. One way is to press the key sequence [INSERT] [Key sequence of instruction] [Key sequence of address].
Page 86 Chapter 4 the instruction will be inserted before the END statement or subroutine area. The other way to insert an instruction is to press the key sequence [INSERT] [ ] [Key sequence of instruction] [Key sequence of address]. The new instruction will be inserted before the cursor’s present position. Bit addresses of 6 or 7 digits can be entered provided the data table is expanded to a 4- or 5-digit word address and the [EXPAND ADDR] key is used.
Page 87 Chapter 4 unlatch instructions are cleared to zero. All other word and bit addresses are not cleared when a rung is removed. Changing Data of a Word or Block Instruction The data of any word or block instruction, except the Arithmetic and Put instructions, can be changed in the program mode without removing and re-entering the instruction.
Page 88 WARNING: The task of on-line programming should be assigned only to an experienced programmer who understands the nature of Allen-Bradley programmable controllers and the machinery being controlled. Proposed on-line changes should be checked and rechecked for accuracy. All possible sequences of machine operation resulting from the change should be assessed in advance.
Page 89 Chapter 4 Block Transfer Read and Write instructions, Jump, Jump to Subroutine, MCR, ZCL and Temp End instructions cannot be inserted. The Label instruction cannot be inserted or removed directly, nor can the rung containing it be removed. However, the Label instruction can be changed to another instruction.
Page 90 Chapter 4 WARNING: When the address of a new instruction duplicates the address of other instructions in the program, the [DATA INIT] key should not be used without first assessing the consequences. Pressing the [DATA INIT] key will zero out the status bits stored at the existing instructions address, which may interfere with desired machine operation.
Page 91 Chapter 4 [RECORD] key is used to enter a change into user program. Once pressed, the changed program is active immediately. [CANCEL COMMAND] key can be used to abort any on-line programming operation prior to pressing the [RECORD] key. It restores the ladder diagram display and program logic to its original state prior to the on-line programming operations.
Page 92 Chapter 4 Step 1 – Press [DISPLAY] 0 or 1 for data monitor mode. Step 2 – Press [SEARCH] 51 for on-line data change. Step 3 – Enter file data, if necessary. Step 4 – Press [CANCEL COMMAND] to terminate on-line data change. Step 5 –...
Page 93 Chapter 4 CAUTION: If the rung logic is true, the output instruction will be enabled immediately. Before pressing the [RECORD] key for the output instruction, verify that each instruction has been entered with no errors. Remove a Rung A completed rung can be removed using the following procedure (refer to Editing, Section 4.4.4, if necessary): Step 1 –...
Page 94 Chapter 4 data has been entered using the data monitor mode. See Insert an Instruction, above. WARNING: When the [RECORD] key is pressed, the substituted instruction is entered into memory immediately. If the rung is true, the output instruction will be enabled and will instantly energize the output device.
Page 95 Chapter 4 The rung will become active immediately. Programming Interruptions If communication between the industrial terminal and processor is interrupted when programming on-line in run/program mode, a rung could be left incomplete (no output instruction). Upon initialization of the industrial terminal, if an incomplete rung is thought to exist, proceed as follows: Step 1 –...
Page 96 Chapter 4 Table 4.E Clear Memory Functions Function Mode Key Sequence Description Data Table Clear Part of all of the data table can be cleared by pressing [CLEAR MEMORY] 77, entering a start and end word address, and then pressing [CLEAR MEMORY] again.
Page 97 Chapter 4 Total Memory Clear The complete memory can be cleared by positioning the cursor on the first instruction of the program and then pressing [CLEAR MEMORY] 99. This resets all the data table bits to zero. A total memory clear should be done before entering the user program.
Page 98 Chapter 4 Figure 4.16 Storage Bit Example Recommendations for Block Instructions Up to 8 condition instructions in series can be programmed in a rung if the output is a block instruction. Up to 8 series condition instructions can be used with a Sequencer Input instruction if the output is not a block instruction.
Page 99 Chapter 4 One series condition instruction can be used with a Sequencer Input and an Examine On or Off Shift Bit in series if the output is a block instruction. Up to 4 Examine On or Off Shift Bit instructions can be used in series if the output is not a block instruction.
Page 100 Chapter Timer and Counter Instructions Timer and Counter instructions are output instructions internal to the processor. They provide many of the capabilities available with timing General relays and solid state timing/counting devices. Usually conditioned by examine instructions, timers and counters keep track of timed intervals or counted events according to the logic continuity of the rung.
Page 101 Both status bits are located in the accumulated value word (Figure 5.2). Figure 5.2 Timer Accumulated Value Word The three types of timers available with the PLC-2/30 processor are: Timer On-Delay –(TON)– Timer Off-Delay –(TOF)– Retentive Timer –(RTO)–...
Page 102 Chapter 5 All three timers differ in the way they set and reset status bits, respond to rung logic continuity and reset the accumulated value. With each timer, the programmer must select one of the following time bases: 1.0 second 0.1 second 0.01 second (10 milliseconds) Bit 16 of the timer accumulated value word reflects the time base.
Page 103 Chapter 5 Figure 5.3 Timer On Delay, Timing Diagram for a Preset Value of 9 Seconds É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É...
Page 104 Chapter 5 5.1.2 The Timer Off-Delay instruction (TOF) can be used to turn a device on or off after a timed interval (Figure 5.4). Like the other timer instructions, Timer Off Delay Instruction the TOF instruction counts time-base intervals and stores this count in its accumulated value.
Page 105 Chapter 5 Figure 5.4 Timer Off Delay, Timing Diagram for a Preset Value of 9 Seconds É É É É É É É É É É É É É É É É É É É É É É É É É...
Page 106 Chapter 5 Figure 5.5 Retentive Timer with Retentive Timer Reset Timing Diagram É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É...
Page 107 Timers can be achieved through special programming techniques described in Programming 0.01 Second Timers With the Mini-PLC-2 Controller Application Data, publication no. 1772-702. Four types of counter instructions are available with the PLC-2/30 Controller: Counter Instructions Up-Controller (CTU) Counter Reset (CTR)
Page 108 Chapter 5 Bit 14 is the overflow/underflow bit. It is set to one when the AC value of the CTU exceeds 999 or the AC value of the CTD goes below 000. Bit 15 (the Done bit) is set to one when a count has been reached or exceeded, that is, when the AC value is PR value.
Page 109 Chapter 5 timer, the CTU instruction continues to increment its accumulated value after the preset value has been reached. If the accumulated value goes above 999, bit 14 is set on to indicate an overflow condition and the CTU continues up-counting from 000. Bit 14 can be examined to cascade counters for counts greater than 999 (Section 5.3).
Page 110 Chapter 5 5.2.2 The Counter Reset (CTR) instruction is an output instruction that resets the CTU accumulated value and status bits to zero. Counter Reset Instruction The counter operates in the same manner as described for the CTU instruction, with the addition of the reset instruction in rung 3 (Figure 5.8). In this example, the reset push button is pressed after count 11.
Page 111 Chapter 5 5.2.3 The Down-Counter (CTD) instruction subtracts one from its Accumulated Value for each false-to-true transition of its rung conditions (Figure 5.9). Down Counter Instruction Because only the false-to-true transition causes a count to be made, rung conditions must go from true to false and back to true before the next count is registered.
Page 112 Chapter 5 Figure 5.10 Up Down Counter Example NOTE: Bit 14 of the Accumulated Value word is set on when the Accumulated Value either overflows or underflows. When a Down-Counter Preset is set to 000, underflow bit 14 is not set on when the count goes below zero.
Page 113 Chapter 5 An individual timer or counter can time or count up to 999 intervals or events. By cascading two or more timers or counters, the timing or Cascading Timers or counting capability within the program can be increased beyond three Counters digits.
Page 114 Chapter 5 The default word address can be 3, 4 or 5 digits provided the data table is sized accordingly. Unlike bit instructions, the [EXPAND ADDR] key is not required. Instead, the industrial terminal automatically enters a 4- or 5-digit default word address depending on the data table size. When a 4- or 5-digit word address is displayed and a 3- or 4-digit word address is required, the programmer must enter leading zeros before the word address.
Page 115 Chapter 5 Table 5.B Timer Instructions NOTE: Keytop Symbol Instruction Name 1770 T3 Display Description Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 116 Chapter 5 Table 5.C Counter Instructions NOTE: Keytop Symbol Instruction Name 1770 T3 Display Description Execution time depends upon the type of instruction, the amount of data operated upon and whether the instruction is true or false. Scan Time and Instruction Execution Times 5.5.1 Scan time is the time required to monitor and update I/O and to execute...
Page 117 Chapter 5 one millisecond, whichever is greater, when a data highway interface module is connected to the processor. 5.5.2 The instruction execution times given in Section 5.6 enable the programmer to estimate scan time for a planned program. The program Program for Determining shown in Figure 5.13 will determine and display the average scan time Scan Time...
Page 118 Figure 5.13 Program for Determining Average Scan Time To enable the programmer to estimate the scan time a proposed program may require, the average execution times required for PLC-2/30 Instruction Execution Time instructions are presented in Tables 5.D through 5.G.
Page 119 Chapter 5 5.6.2 Table 5.E contains longer execution times for more complicated instructions. Note that all of the Table 5.E instruction execution times are Word to File, Sequencers, affected by file lengths and are longer for larger files. FIFO, Word and Bit Shifts, File Diagnostic, File Search, Other factors affecting execution are explained below for specific instructions.
Page 120 Chapter 5 Table 5.D Average Execution Times for Instructions Described In Chapters 3 Through 8 When Instruction is TRUE Execution Time in Instruction Name Symbol Microseconds Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 121 Chapter 5 Table 5.E Average Execution Times for Word To File, Sequencers, Word and Bit Shifts, File Diagnostic, File Search and Block Transfer Instructions Average Execution Time in Microseconds False True Instruction 5.6.3 Table 5.F presents average instruction execution times for File-to-File move and File Complement instructions for the distributed complete, File to File Move and File complete and incremental modes.
Page 122 Chapter 5 As an example, we will calculate the execution time for File-to-File move in the distributed complete mode for the following conditions: Rate per scan = 256 words operated upon per scan. File length = 542 words 542 words in file = two full 256 word blocks + 30 words. Therefore, use 2 for the number of blocks operated upon per scan and ignore the +30 words.
Page 123 Chapter 5 The execution time, T, in microseconds for the complete mode is: T = 99 + 9.8 (Words operated upon per scan) + 14.4 (Number of 256 word blocks operated upon per scan) Example: What is the execution time to perform a File-to-File AND operation on two files 670 words long? The rate per scan is 256 and the mode is the distributed complete mode.
Page 124 Chapter Data Manipulation Instructions The data manipulation instructions are used to transfer or compare data that is stored in data table words and bytes. There are six data manipulation General instructions: GET –|G|– PUT –(PUT)– LES –|<|– EQU –|=|– GET BYTE –|B|– LIMIT TEST –|L|–...
Page 125 Chapter 6 The Get Byte and Limit Test instructions compare 3-digit values in octal format using eight bits (one byte) of a data table word (Figure 6.2). This 3-digit value is an octal number ranging from 000 to 377 . Note that two 3-digit values can be stored in a word: one in the upper byte (bits 10-17) and one in the lower byte (bits 00–07).
Page 126 Chapter 6 Figure 6.3 Get and Put Instructions If the word addressed by a Get instruction already contains data, the lower 12 bits of the data are displayed automatically after the word address is entered. Entry of new data, such as a new BCD value, writes over the data previously stored in the addressed word.
Page 127 Chapter 6 Figure 6.4 Changing a Counter Preset NOTE: The lower 12 bits of transferred data are displayed in BCD beneath the Put instruction. Bits 14-17 are not displayed but are transferred. While the rung is true, any change in the data of the Get instruction also changes the data of the Put instruction.
Page 128 Chapter 6 A Get/Les or Get/Equ pair of instructions forms a single condition for logic continuity. Alone or with other conditions, each pair can be used to energize an output device or other output instruction. In all cases, the Get instruction must be programmed before the Les or Equ instruction.
Page 129 Chapter 6 Figure 6.6 Greater Than Comparison Equal To – An equal-to comparison is made with the Get and Equ instructions (Figure 6.7). The Get value is the changing variable and is compared to the reference value of the Equ instruction for an equal-to condition.
Page 130 Chapter 6 Figure 6.8 Less Than or Equal To Comparison Greater Than or Equal To – This comparison is made using the Get, Les and Equ instructions. The Get value is assigned a reference value. The Les and Equ values are changing values that are compared to the Get value (Figure 6.9).
Page 131 Chapter 6 logic continuity. Condition instructions can be programmed before the Get Byte instruction or after the Limit Test instruction, but not between them (Figure 6.10). Figure 6.10 Get Byte/Limit Test Comparison The Get Byte instruction addresses either the upper or lower byte of a data table word.
Page 132 Chapter 6 The Get Byte instruction addresses either the upper or lower byte of a data table word. A 1 is entered after the word address for an upper byte; a 0 is entered for the lower byte. Figure 6.11 Get Byte-Put Instruction The Data Manipulation instructions are programmed from the industrial terminal keyboard with the processor in the program mode.
Page 133 Chapter 6 Table 6.A Data Manipulation Instructions NOTE: Keytop Symbol Instruction Name 1770 T3 Display Description Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 134 Chapter 6 The PLC-2/30 processor can be programmed to perform arithmetic operations with two BCD values using a set of arithmetic instructions and Arithmetic Instructions can perform conversions from 12-bit binary to BCD and vice versa. These output instructions are: Add –(+)–...
Page 135 Chapter 6 Figure 6.12 Arithmetic Instruction Word The conversion instructions are in block format. They don’t require Get instructions. The 12-bit binary value is stored in one word and the BCD value is stored in two consecutive data table words. Any condition instructions can be programmed before a conversion instruction.
Page 136 Chapter 6 Figure 6.13 Add Instruction 6.4.2 The Subtract instruction tells the processor to subtract the second Get word value from the first Get word value (Figure 6.14). The difference is then Subtract Instruction stored at the data table word addressed by the Subtract instruction. If the difference is a negative number, the underflow bit of the Subtract word (bit 16) is set on.
Page 137 Although division by 0 is undefined mathematically, the following results are obtain with a PLC-2/30 PC processor when dividing by 0: 0 = 001.000, 1 to 999 0 = 999.999 This differs from the Mini-PLC-2 and the Mini-PLC-2/15 where 0 999.999.
Page 138 Chapter 6 Figure 6.16 Divide Instruction Arithmetic instructions are entered into memory with the PLC-2/30 Processor in the program mode. When entered, these instructions will be Programming Arithmetic intensified and blinking. They will continue to blink until the word address Instructions is entered.
Page 139 Chapter 6 Table 6.B Arithmetic Instructions NOTE: Keytop Symbol Instruction Name 1770 T3 Display Description Important: This note applies to BCD to Binary and Binary to BCD conversions. A BCD-to-Binary or Binary-to-BCD conversion is performed on the lower twelve bits of a word. The upper four bits are not involved with the conversion and are not transferred.
Page 140 Chapter 6 If the BCD value is > 4095, the overflow bit (bit 14 of the binary address) will be set on. The binary number result will be stored in the lower 12 bits (00-13) of a word selected by the user. 6.6.1 To program a BCD to Binary conversion, press keys [CONVERT] 0.
Page 141 Chapter 6 DATA – The BCD number is 004095 (the largest BCD number that can be converted to a 12-bit binary number). BINARY ADDR – Data Table word 025 DATA – The industrial terminal will display 12 ones (1), the binary representation of the decimal number 004095.
Page 142 Chapter 6 BINARY ADDR – 125 DATA – 111111111111 ADDR – The BCD number is stored in adjacent data table words 200 and 201 DATA – The industrial terminal will display 004095, the BCD equivalent of the binary value for this example. Figure 6.19 Binary to BCD Conversion Format BINARY TO BCD...
Page 143 Chapter 6 Figure 6.20 Binary to BCD Conversion Example Rung BINARY TO BCD (OV) BINARY ADDR: DATA: 111111111111 ADDR: 201- 202 DATA: 004095 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 144 Emergency stop switches can be monitored but should not be controlled by the user program. These devices should be wired as described in the PLC-2/30 Assembly and Installation Manual, publication no. 1772-805. To override a group of output devices, two MCR or ZCL instructions are required: one to begin the zone and one to end the zone (Figure 7.1).
Page 145 Chapter 7 Figure 7.1 MCR and ZCL Zone Programming The MCR and ZCL instructions control the zoned outputs differently: MCR — When false, all nonretentive outputs within the MCR zone are de-energized or turned off. ZCL — When false, the outputs within the ZCL zone are left in their last state: either on or off.
Page 146 Most electromechanical devices have a response time longer than the processor scan time. Thus, data to and from these devices need not be updated ahead of the normal I/O scan. 7.2.1 The PLC-2/30 processor scan sequence can be divided into 2 parts (Figure 7.2): Scan Sequence Program Scan I/O Scan Artisan Technology Group - Quality Instrumentation ...
Page 147 Chapter 7 Figure 7.2 Scan Sequence Upon power up, the processor begins the scan sequence with the program scan and then the I/O scan. During the I/O scan, data from the input modules is transferred to the input image table. Data from the output image table is transferred to the output modules.
Page 148 Chapter 7 7.2.2 The Immediate Input instruction updates one word of the input image table data in advance of the normal scan sequence (Figure 7.3). The image table Immediate Input Instruction word represents one module group in the I/O chassis. The Immediate Input instruction is programmed in the condition area of the ladder diagram rung.
Page 149 Chapter 7 7.2.3 The Immediate Output instruction updates one module group with data from one output image table word ahead of the normal scan sequence Immediate Output (Figure 7.4). Instruction The Immediate Output instruction is programmed as an output instruction in the ladder diagram rung.
Page 150 Chapter 7 Figure 7.4 Immediate Output Instruction É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É...
Page 151 Chapter 7 The Immediate I/O instructions are programmed with the processor in the program mode. When entered from the industrial terminal, they will Programming Immediate I/O be displayed as intensified and blinking with the reverse-video cursor Instructions positioned on the first digit of the default word address. The number of digits in the default address can range from 4 to 5 depending on data table size.
Page 152 One 64-I/O chassis and two 32-I/O chassis Four 32-I/O chassis The PLC-2/30 can control up to 14 I/O racks when using the 1772-SD2 distribution panel. For information on wiring, switch settings and use of the 1772-SD2 distribution panel, refer to the Allen-Bradley Remote I/O Scanner/Distribution Panel Product Data (publication no.
Page 153 Chapter 7 Figure 7.5 Remote I/O Configuration Example Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 154 Chapter 7 Fault zones can be programmed around certain parts of the program or the entire program using fault status bits and MCR or ZCL zones. The fault status bits used for remote fault zone programming are located in data table words 125 and 126 (Table 7.B).
Page 155 Chapter 7 Each fault status bit within a group of four corresponds to two consecutive module groups of 32 I/O points (Table 7.B). When a fault occurs in a remote rack, one or more of the four status bits are set on depending on the configuration of the I/O rack.
Page 156 Chapter 7 NOTE: If a fault occurs in a local rack, all racks will behave according to their last state switch whether dependent or independent mode has been selected. 7.4.2 Independent fault zone programming is used to zone off independent sections of user program.
Page 157 Chapter 7 Figure 7.7 Separate Independent Fault Zone Programming for Individual I/O Chassis Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 158 Chapter 7 Figure 7.8 Alternate Independent Fault Zone Programming for Individual I/O Chassis The time required to perform scans of I/O differs depending upon whether the I/O racks are local or remote. I/O Update Times 7.5.1 The scan time for local systems is 0.5 ms per rack. Local Systems 7.5.2 The scan time for remote systems depends upon the baud rate for which...
Page 159 Chapter 7 The 1772-SD2 scans remote I/O racks and stores the information in its buffer. The processor, during the I/O scan, updates any local I/O racks and then gets the information from the 1772-SD2 buffer. This information in the buffer may be combination of new and old data depending on where the 1772-SD2 was in its scan when the processor requested the information.
Page 160 Chapter 7 Table 7.C Average Execution Times in Microseconds for FILE TO FILE AND, OR, XOR Instructions when Instruction is True Rate Per Scan Dist. Complete Mode Complete Mode Table 7.D The Following Instructions Reset the Watchdog Timer Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 161 Chapter Peripheral Functions There are several functions that can be performed with a PLC-2/30 and the industrial terminal. Some require the use of a peripheral divide connected General to channel C of the industrial terminal. The functions include: Contact histogram...
Page 162 Chapter 8 Peripheral Functions Channel C must be on to receive input from a peripheral device. It is initially on. It can be toggled on/off by pressing [RECORD] 9 (Channel C status display) and pressing 2. Table 8.B Key Sequence for Setting Baud Rate Key Sequence Baud Rate [RECORD] [2]...
Page 163 Chapter 8 Peripheral Functions Table 8.C Contact Histogram Functions Function Mode Key Sequence Description Contact Histogram [SEARCH] [6] Provides a continuous display of the ON/OFF history of the Continuous RUN/PROGRAM [Bit Address] addressed bit in hours, minutes, and seconds. or TEST [DISPLAY] Can obtain a hardcopy printout of contact histogram by connecting a peripheral device to Channel C and selecting...
Page 164 Chapter 8 Peripheral Functions The industrial terminal screen can display up to 11 lines of data at one time. In the continuous mode, the screen will automatically display a new page of data when the screen is full. In the paged mode, 11 lines will fill the screen and stop. Subsequent changes are stored in the buffer until [DISPLAY] is pressed.
Page 165 Chapter 8 Peripheral Functions The cassette load command is accessed by pressing [RECORD] 0 on the PLC-2 family overlay and by pressing either [READ FROM TAPE] or [PLAY] on the cassette recorder. To load the complete memory, rewind the tape to the beginning of the program. As memory is being loaded, the number of data table words and program words will be counted and displayed.
Page 166 Chapter 8 Peripheral Functions 8.3.5 During automatic or program verification, the processor will identify discrepancies between memory content and the content on the cassette Displaying and Locating tape. By pressing [SEARCH] 9 on the PLC-2 family overlay, the number Errors of program and data table discrepancies found and whether or not the data table was verified will be displayed.
Page 167 Chapter 8 Peripheral Functions As memory content is being recorded on tape, the industrial terminal will count the number of user program and data table words and display them as follows: ABCD Program Words EFGH Data Table Words After memory content has been recorded, the tape is automatically rewound and the content verified with the content in memory to be sure that no discrepancies occurred during the recording operation.
Page 168 Chapter 8 Peripheral Functions 8.4.3 This command is used to verify user program and messages in processor memory with the content in data cartridge tape, or vice versa. Although the Data Cartridge Verification data table size and configuration are checked, the data table content is not verified.
Page 169 Chapter 8 Peripheral Functions The data table printout will be followed by the user program in ladder diagram and block format. The messages will be printed out and identified by number. When the printout is complete, this command is automatically terminated. The total memory dump command can be terminated prior to completion by pressing [ESC] on the peripheral printer or [CANCEL COMMAND] on the PLC-2 family overlay.
Page 170 Chapter Report Generation The report generation function of the T3 industrial terminal, performed in the PLC-2 mode, can be used to generate messages that contain ASCII and General graphic characters, and variable data table information. The messages are stored in the processor’s memory after the END of program statement. We also have a PLC-2 Family Report Generation Module (Cat.
Page 171 Chapter 9 Real-time calendar – you can enter and display the date, and use the date in a message. Date format is month/day/year — July 16, 1984 is 7/16/84. Peripheral fault detection – module sets bit 027/06 in the processor data table when the module detects a fault in the peripheral device Module reconfiguration –...
Page 172 Chapter 9 Figure 9.1 Alphanumeric Keytop Overlays The report generation function is entered by pressing [RECORD] [DISPLAY] on the PLC-2 Family keytop overlay. There are 6 report Report Generation generation commands used to enter control words and to store, print, report Commands and delete messages and to display an index of existing messages.
Page 173 Chapter 9 Table 9.A Report Generation Commands Command Key Sequence Description 9.1.1 Bits from eight consecutive user-selected words control the 64 additional messages (1770-FD Series B and all its subsequent revisions). Message Control Word File - MS, 0 The eight message control words are determined by establishing a 2-word message in memory, called message 0.
Page 174 Chapter 9 the industrial terminal will also display a table (Table 9.B) which shows the message numbers associated with each message control word. Table 9.B Example Message Control Word Message Number Relationship Control Words Message Numbers NOTE: 9.1.2 Accessible only in the program mode, this command is used to enter messages in memory.
Page 175 Chapter 9 Table 9.C Address Delimiters Delimiter Format Explanation Message Report Format As an example, suppose it was desired to report the output condition, or or off, of a device, SR6, during each cycle of machine operation. Delimiters would be used to denote the output address 013/05, and the cycle counter accumulative value (stored at 030 ).
Page 176 Chapter 9 The message print command is self-terminating. [ESC] or [CANCEL COMMAND] can be used to return to ladder diagram display. 9.1.4 Accessible in any mode, the message report command is used to print a message with the current data table value or bit status that corresponds to Message Report - MR an address between the delimiters.
Page 177 Chapter 9 The T3 industrial terminal screen size is an 80 x 24 format: 80 columns across by 24 lines down. An example message using graphic and alphanumeric characters is shown in Figure 9.2. The control code, [CTRL] [P] [Column #] [;] [Line #] [A], should be used for cursor positioning to conserve memory when possible.
Page 178 Chapter 9 Table 9.D Alphanumeric/Graphic Keytop Definitions Function Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 179 Chapter 9 Table 9.E Industrial Terminal Control Codes Control Code Key Sequence Function Key Sequence Attribute Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 180 Chapter 9 Table 9.F ASCII Control Codes Control Code Display ASCII Mnemonic Name The processor will go into manual mode if the keyswitch is in the PROG position. If the processor keyswitch is changed to the PROG position, the Manually Initiated Report processor will automatically change from automatic to manual report Generation generation mode.
Page 181 Chapter 9 Messages can be printed through program control automatically be energizing specific message request bits using output latch and output Automatic Report unlatch instructions. Generation Automatic report generation can be accessed if the keyswitch is in the TEST, RUN, or RUN/PROGRAM position by pressing [SEARCH] 40 or by pressing [M] [R] [RETURN].
Page 182 Chapter 9 9.3.1 Messages 1-6 use bits 10-15 of word 027 as message request bits. All other messages use a user-defined file of message request bits for control. These Messages 1 6 two categories will be discussed separately. The upper byte of word 027 is used to control messages 1-6. Bit 027/10 is the request bit for message number 1;...
Page 183 Chapter 9 Figure 9.5 Message Request Bit Done Bit Relationship The message print command is valid for message 0. It will print out the message control word addresses such as tabular form shown in Table 9.B. If the location of the message control file is to be changed or if message 0 is no longer needed, it can be deleted with the message delete command and re-entered at any time.
Page 184 Chapter 9 Figure 9.6 Example Program to Request a Message Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 185 Chapter Block Transfer 10.0 Block transfer is a combination of an instruction and support rungs used to transfer up to 64 16-bit words of data in one scan from I/O modules General to/from the data table. It is used with intelligent I/O modules such as the analog, PID, servo positioning, stepper positioning, ASCII, thermocouple, or encoder/counter modules which have this capability.
Page 186 Chapter 10 Block Transfer Figure 10.1 Module Position Image Table Byte Relationship Data Table I/O Rack Bit Numbers 10 07 Output Image Output Image Table Table Word, Lower Byte É É É É É É Control Byte Block Transfer É É É É É É Module Input Image Table Input Image...
Page 187 Chapter 10 Block Transfer Figure 10.2 Block Transfer Diagram Transfer is made in I/O Scan Output Input Scan Scan Request is made in Program Scan Once the module address is found, the processor locates the address of the file to which (or from which) the data will be transferred. The file address is stored in BCD at an address 100 above the address containing the module address.
Page 188 Chapter 10 Block Transfer 10.2 The format of a block transfer read and a block transfer write instruction with default values is shown in Figure 10.3. Block Transfer Instructions Figure 10.3 Block Transfer Format BLOCK XFER READ (EN) DATA ADDR MODULE ADDR BLOCK LENGTH FILE...
Page 189 Chapter 10 Block Transfer Table 10.B The First Available Address in Timer/Counter Area of Data Table # I/O Racks First Available Address in Timer/Counter Area The module address is stored in BCD by r=rack, g=module group and s=slot number. When block transfer is performed, the processor searches the timer/counter accumulated area of the data table for a match of the module address.
Page 190 Chapter 10 Block Transfer 10.2.4 The read and write bits are the enable bits for block transfer modules. Either one (or both for a bidirectional transfer) is set on in the program Enable Bit and Done Bit scan when the rung containing the block transfer instruction is true. The done bit is set on in the I/O scan that the words are transferred, provided that the transfer was initiated and successfully completed.
Page 191 Chapter 10 Block Transfer Figure 10.4 Data Table Locations for a Block Transfer Read Instruction Data Table Output Output image table byte Image Block Length contains read enable bit Table Code and block length in binary code. Data address contains module address in BCD.
Page 192 Chapter 10 Block Transfer During the program scan when input switch 113/02 is closed, the instruction is enabled and read bit 012/17 is set to 1. In the next scan of the output image table, the upper byte data of word address 012 is sent to the module.
Page 193 Chapter 10 Block Transfer WARNING: When programming multiple writes (or reads) to the same module, it is possible that a desired transfer will not take place or the number of words transferred will not be the number intended. Invalid data could be sent to an analog output device (or could be operated upon in subsequent scans) resulting in unpredictable and/or hazardous machine operation.
Page 194 Chapter 10 Block Transfer Figure 10.5 Programming Multiple Reads from One Module Inputs BLOCK TRANSFER READ | / | | / | (EN) DATA ADDR MODULE ADDR BLOCK LENGTH (DN) FILE 160 167 Inputs BLOCK TRANSFER READ | / | | / | (EN) DATA ADDR...
Page 195 Chapter 10 Block Transfer 10.7 When the block transfer instructions are used, the first word and consecutive words of the timer/counter accumulated area of the data table Defining the Block Transfer must be reserved for block transfer data addresses. Data Address Area Block transfer data addresses should be separated from the addresses of timer and counter instructions by inserting a boundary.
Page 196 Chapter 10 Block Transfer 10.8 The purpose of block transfer data buffering is to allow the data to be validated before it can be used. Data that is read from the block transfer Buffering Data module and transferred to data table locations must be buffered. Data that is written to the module need not be buffered because block transfer modules perform this function internally.
Page 197 Chapter 10 Block Transfer Figure 10.7 Buffering Data Block Length Code Data in the buffer file 050 052 will be moved to 150 152 when: A. Done Bit 114/07 is set (valid transfer) B. Diagnostic Bit is TRUE for each word to be moved in rungs 5 7 Block Transfer Data (Buffer) (valid data)
Page 198 Chapter 10 Block Transfer Block Transfer will be enabled during the program scan. The transfer will be performed during an interruption of the next I/O scan. Data from the module will be loaded into words 050-052. When block transfer is complete, done bit 114/07 is set in the input image table byte.
Page 199 Chapter 10 Block Transfer The data table locations and block instructions for this example are shown in Figure 10.8. 10 15 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 200 Chapter 10 Block Transfer Figure 10.8 Data Table Locations for Bidirectional Block Transfer Data Table Block Length Output Image Table Low Byte Code Data Addresses 5 words of data table are to be written to the bidirectional block transfer modul starting form word 050 Block Transfer Write File 5 words of data are to be read from the module and loaded into the data...
Page 201 Chapter 10 Block Transfer 10.9.2 The module address is stored in BCD in the data address of the read and write instructions. In this example, the module address is 130: rack 1, Data Address and Module module group 3, slot 0. Address Two data addresses must be used.
Page 202 Chapter 10 Block Transfer 10.9.5 The programming of a bidirectional block transfer module depends on whether the read and write instruction block lengths are equal or unequal. Programming Considerations Equal Block Lengths When the block lengths are set equal or when the default block length is specified by the programmer, the following considerations are applicable: Read and write instructions could and should be enabled in the same scan (separate but equal input conditions).
Page 203 Chapter Jump Instructions and Subroutine Programming 11.0 The Jump instruction and subroutine programming allow programming flexibility and efficiency. Four instructions are used to implement program General jumps and subroutines: Jump – JMP Label – LBL Jump to Subroutine – JSR Return –...
Page 204 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.1 JUMP Format ( JMP ) XX = Octal Identification Number Figure 11.2 JUMP to LABEL Operation | / | ( JMP ) -| |- When is true, program execution jumps to label 07. | / | ( TON ) PR 999...
Page 205 Chapter 11 Jump Instructions and Subroutine Programming Instruction overview: Output instruction Can jump 1 or more times to the label with the same identification number. Uses 1 word of memory Has 2 digit octal identification number Caution is advised when jumping over timers or counters. Causes of run-time errors: NOTE: Do not misuse the Jump instruction.
Page 206 Chapter 11 Jump Instructions and Subroutine Programming Table 11.A Jump/Subroutine Programming Key Symbol Instruction Name 1770 T3 Display Description SUBROUTINE AREA SUBROUTINE AREA Establishes the boundary between Main Program and T.END Subroutine Area. Subroutine Area is not scanned unless directed to do so by a JSR instruction. LABEL This condition instruction is the target destination for JMP -(JMP)-...
Page 207 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.4 Multiple JUMPS to LABEL in Subroutine Area From Subroutine Area JSR 03 (1st Subroutine) ( JMP ) ( RET ) From JSR 04 (2nd Subroutine) ( JMP ) To Main Program ( RET ) 11 5 Artisan Technology Group - Quality Instrumentation ...
Page 208 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.5 Multiple JUMPS to LABEL in Subroutine Area and Multiple Return Paths to Main Program Main Program | / | ( JSR ) Subroutine Area ( JSR ) (Subroutine) ( JSR ) ( RET ) 11.2 The Label instruction shown in Figure 11.6 is the target destination for...
Page 209 Chapter 11 Jump Instructions and Subroutine Programming The Label instruction is always logically true. It should be programmed as the first condition instruction in the rung. If conditions precede a Label instruction in a rung, they will be ignored by the processor during a jump operation.
Page 210 Chapter 11 Jump Instructions and Subroutine Programming enables a subroutine to call itself or loop. This will be explained in Section 11.3.3. Instruction overview: Output instruction Must always jump from main program into subroutine area or from one subroutine to another Can jump 1 or more times to the label with the same identification number Uses 1 word of memory...
Page 211 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.8 JUMP TO SUBROUTINE LABEL Operation | / | ( JSR ) -| |- When is true, program execution jumps to subroutine label 06. ( TON ) PR 999 AC 000 ( RET ) At the end of subroutine program, execution returns to user program at next instruction after subroutine...
Page 212 Chapter 11 Jump Instructions and Subroutine Programming 11.3.1 The area reserved for subroutines is located in memory between the main program and the message store areas. Its boundary is displayed as Subroutine Area subroutine area, and serves as the end of program statement for the main program.
Page 213 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.9 Representative Subroutine Area Main Program | / | Subroutine Area Subroutine boundary serves as end statement for main The label is the first | / | program. instruction in each subroutine. (Subroutine #1) ( RET ) (Subroutine #2)
Page 214 Chapter 11 Jump Instructions and Subroutine Programming 11.3.3 A subroutine can loop or call itself (Figure 11.10b). If this procedure is used, it is recommended that a scan counter be used to ensure that a Recursive Subroutine maximum of 9 JSR’s (including the original one in the main program) is (Looping) Calls not exceeded.
Page 215 Chapter 11 Jump Instructions and Subroutine Programming Figure 11.10 (a) Three Levels of Nested Subroutines (b) A Subroutine Can Call Itself or Loop (A.) Subroutine Area Subroutine Subroutine Subroutine Level 1 Level 2 Level 3 Main Program ( JSR ) ( JSR ) ( JSR ) ( RET )
Page 216 Chapter 11 Jump Instructions and Subroutine Programming 11.4 The Return instruction is an output instruction (Figure 11.11). It is used only in the subroutine area to terminate a subroutine and to return program Return Instruction execution to the main program (Figure 11.8) or, in the case of nested subroutines, to return program execution to the preceding subroutine (Figure 11.11).
Page 217 Chapter Data Transfer File Instructions 12.0 This chapter introduces concepts in two major areas: General Files Data monitor mode Later chapters of this manual are written with the assumption that the concepts and terms covered in this chapter have been thoroughly learned. In particular, do not proceed into Chapters 13-17, File, Sequencer, and Shift Register instructions, until this chapter is completely understood.
Page 218 Chapter 12 Data Transfer File Instructions Figure 12.1 File Structure Counter Addr: 200 File Length - 012 = Preset Value Starting Address of File: 600 Position = 005 = Accumulated Value Position Word Address É É É É É É É É É É É É Current Word Being É...
Page 219 Chapter 12 Data Transfer File Instructions Figure 12.2 File Instruction Format FILE-TO-FILE MOVE (EN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110- 110 (DN) FILE R: 110- 110 RATE PER SCAN: Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 220 Chapter 12 Data Transfer File Instructions Externally Indexed Counter When the counter is externally indexed, the accumulated value must be positioned to point to a word in the file by instructions in the user program. The counter can be indexed randomly by using a Get/Put transfer or sequentially by using another counter.
Page 221 Chapter 12 Data Transfer File Instructions Figure 12.4 Example of an Internally Indexed File Instruction FILE-TO-FILE MOVE (EN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 512- 527 (DN) FILE R: 562- 577 RATE PER SCAN: Notice that another term has been added to the instruction block: rate per scan.
Page 222 Chapter 12 Data Transfer File Instructions Figure 12.5 Complete Mode Operation Data Table One Scan Rate Per Scan = 14 = File Length. Entire file is operated upon in 1 scan. Operation goes to completion after a single false 14 Word to true transition of the rung condition.
Page 223 Chapter 12 Data Transfer File Instructions Figure 12.6 Status Bits for Complete Mode Scan Rung Condition Enable Bit (17) Done Bit (15) A = Status bits are reset to zero and counter is reset to word 1. Instruction Operation Distributed Complete Mode In cases where is is not necessary that the file operation be completed in one program scan, it may be advantageous to distribute the file operation over several program scans.
Page 224 Chapter 12 Data Transfer File Instructions Figure 12.7 Distributed Complete Mode Operation Data Table Scan #1 5 Words Scan #2 Scan #1 5 Words Scan #3 Scan #2 Remaining 4 Words Rates Per Scan = 005 Scan #3 File is operated upon over 3 scans. Operation goes to completion after a single false to true transition of the rung condition.
Page 225 Chapter 12 Data Transfer File Instructions Figure 12.8 Status Bits for Distributed Complete Mode More than 1 Scan Rung Condition Enable Bit (17) Done Bit (15) Instruction Operation A = Status bits are reset to zero and counter is reset to word 1. a) Rung is True at completion.
Page 226 Chapter 12 Data Transfer File Instructions Incremental Mode The incremental mode allows the file to be operated upon one word per rung transition. Each time the rung containing the instruction goes from false to true, the instruction operates on the word pointed to by the counter accumulated value, and then increments to the next word.
Page 227 Chapter 12 Data Transfer File Instructions scans equal to the file length. In the incremental mode (r = 0), the operation must be enabled by a separate false-true transition for each word in the file. The operation of the status bits in the incremental mode is illustrated in Figure 12.10.
Page 228 Chapter 12 Data Transfer File Instructions entered. Default values are presented in the instruction block. A character cursor will indicate where instruction parameters are to be entered. The programming and operation of the block instructions are covered in detail in the section specifically assigned to each instruction. 12.1.5 If the counter accumulated value exceeds its preset value, the instruction counter will be indexed outside the file.
Page 229 Chapter 12 Data Transfer File Instructions Figure 12.11 FILE TO FILE MOVE Operation Move 10 word file (starting at location 410) to 10 word file (starting at location 474). File A (10 words) File R (10 words) Instruction overview: Output instruction Key sequence: [FILE] 10 Requires 5 words of user program Can operate in incremental, distributed complete, or complete modes...
Page 230 Chapter 12 Data Transfer File Instructions 12.2.1 Programming File to File Move Instructions WARNING: The counter address for the File-to-File move instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or a run-time error.
Page 231 Chapter 12 Data Transfer File Instructions COUNTER ADDR – 200 POSITION (set by instruction) – 001 FILE LENGTH – 010 FILE A – starts at 410 and ends at 421 FILE R – starts at 474 and ends at 505 RATE PER SCAN –...
Page 232 Chapter 12 Data Transfer File Instructions Figure 12.14 FILE TO WORD MOVE Operation Words within file A (starting at location 474) are moved to word 400. Counter 200: PR = 010 AC = 005 Word W File A Value at 5th location in file (10 words) (word 500) will be moved to word 400.
Page 233 Chapter 12 Data Transfer File Instructions Figure 12.15 FILE TO WORD MOVE Format FILE-TO-WORD MOVE (DN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110- 110 WORD ADDRESS: Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 234 Chapter 12 Data Transfer File Instructions Figure 12.16 FILE TO WORD MOVE Example Rung FILE-TO-WORD MOVE (DN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 474- 505 WORD ADDRESS: 12.4 This output instruction transfers a duplicate of the value in a specified data table word W (Figure 12.17) into a word in file R that is pointed to by the Word to File Move counter accumulated value.
Page 235 Chapter 12 Data Transfer File Instructions Figure 12.17 WORD TO FILE MOVE Operation Value in word 500 moved into indexed position within file R (starting at location 474). Counter 050: PR = 010 AC = 005 Word W File R Value at word 400 will be moved (10 words) into 5th location of file, specifically...
Page 236 Chapter 12 Data Transfer File Instructions Figure 12.18 WORD TO FILE MOVE Format WORD-TO-FILE MOVE (DN) COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDRESS: FILE R: 110- 110 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 237 Chapter 12 Data Transfer File Instructions Figure 12.19 WORD TO FILE MOVE Example Rung WORD-TO-FILE MOVE (DN) COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDRESS: FILE R: 474- 505 12.5 The data monitor mode can be used to monitor, load and edit data. Each file instruction has two corresponding data monitor displays.
Page 238 Chapter 12 Data Transfer File Instructions Table 12.B Accessing the Display Key Sequence Explanation [DISPLAY] X Accesses data monitor format. [DISPLAY] X [RECORD] Prints first 20 lines of the data monitor. [DISPLAY] X [HELP] Accesses the ASCII/Hexadecimal conversion table. [DISPLAY] X [HELP] Prints the ASCII/Hexadecimal conversion table.
Page 239 Chapter 12 Data Transfer File Instructions Figure 12.20 Example Hexadecimal Data Monitor Display of File Instruction HEXADECIMAL DATA MONITOR FILE TO FILE MOVE COUNTER ADDR: 031 POSITION: 001 FILE LENGTH: 035 FILE A: 200 242 FILE R: 300 342 POSITION FILE A DATA FILE R DATA A4B2...
Page 240 Chapter 12 Data Transfer File Instructions 12.5.2 Data monitor displays, although unique for each File instruction, have common characteristics including a header section, a file section and a Data Monitor Display command buffer. Header The header is located at the top of the screen and contains information pertinent to its corresponding File instruction, such as: counter address, file addresses, current position value and length value.
Page 241 Chapter 12 Data Transfer File Instructions The command buffer is always displayed when the processor is in program mode. When in run/program mode, the command buffer will not be displayed unless the on-line data change feature is being used. 12.5.3 The field cursor and digit cursor are used together to enter or change file data.
Page 242 Chapter 12 Data Transfer File Instructions Digit Cursor The digit cursor initially appears in the left-most position in the command buffer. It can be moved to the right or left within the command buffer by pressing the [ ] or [ ] cursor command keys, respectively. It will not respond to a command to move outside the buffer area.
Page 243 Chapter 12 Data Transfer File Instructions Table 12.E Paging and Specified Paging Key Sequence Explanation [SHIFT] [ ] Displays the next full page of data. [SHIFT] [ ] Displays the previous full page of data. [DISPLAY] [X] [X] [X] Specified paging presents a page beginning at the desired file word XXX.
Page 244 Chapter 12 Data Transfer File Instructions Table 12.F Data Entry Commands Key Sequence Explanation [D] [D] [D] [D] Data is entered or changed in the Command Buffer. [INSERT] Command Buffer data is loaded into Processor memory and placed into the file word located by the Field Cursor. [CANCEL COMMAND] Terminates Data Monitor Mode and returns display to Ladder Diagram.
Page 245 Chapter Shift Register Instructions 13.0 The file shift instructions are: General Shift File Up Shift File Down FIFO Load FIFO Unload The first two output instructions are used to construct synchronous word shift registers from 1 to 999 words long (Figure 13.1). Upon false-true transition of rung decision, the data from input word will be shifted into the file, and the data in the last/first word of the file will be shifted up/down into the output word.
Page 246 Chapter 13 The FIFO Load and FIFO Unload output instructions that are always used together to construct an asynchronous word shift register (Figure 13.2) up to 999 words long. Upon false-true transition of rung decision, the contents of the input word will be transferred into the stack (FIFO Load); or the contents of the word designated by the unload pointer will be transferred to the output word (FIFO Unload).
Page 247 Chapter 13 input word of data and to shift out one word of data to the output word. The output word data should NOT be considered valid until the bit is set. Instruction overview: Output instruction Key sequence: [SHIFT REG] 10 Counter manipulated by instruction Can operate in distributed complete or complete modes Requires 6 words of user program...
Page 248 Chapter 13 Figure 13.3 SHIFT FILE UP Format SHIFT FILE UP (EN) COUNTER ADDR: FILE LENGTH: FILE: 110- 110 INPUT ADDR: (DN) OUTPUT ADDR: RATE PER SCAN: Figure 13.4 shows the format of Figure 13.3 after the following conditions have been entered. COUNTER ADDR –...
Page 249 Chapter 13 Figure 13.4 SHIFT FILE UP Example Rung SHIFT FILE UP (EN) COUNTER ADDR: FILE LENGTH: FILE: 400- 477 INPUT ADDR: (DN) OUTPUT ADDR: RATE PER SCAN: 13.2 This instruction can be used as a synchronous word shift register. When the rung goes true, the data from a specified input word is shifted into the last Shift File Down word file (Figure 13.1b), the data in the file is shifted down one word...
Page 250 Chapter 13 To program a Shift File Down instruction press keys [SHIFT] [REG] 11. The format that appears and the technique for insertion of numbers, will be identical to that for Shift File Up (Figures 13.3 and 13.4) except that the title will read Shift File Down.
Page 251 Chapter 13 Figure 13.5 Format for FIFO LOAD and FIFO UNLOAD Instructions FIFO UNLOAD (EN) COUNTER ADDR: FIFO SIZE: NUMBER IN FILE: (FL) FILE: 110- 110 INPUT ADDR: INPUT DATA: 0000 (EM) FIFO LOAD (EN) COUNTER ADDR: FIFO SIZE: NUMBER IN FILE: (FL) FILE: 110- 110...
Page 252 Chapter 13 13.3.1 Programming FIFO Load and FIFO Unload Instruction WARNING: The counter address specified for FIFO Load and FIFO Unload instructions should be reserved for these instructions. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or run-time error.
Page 253 Chapter 13 Figure 13.6 FIFO LOAD and FIFO UNLOAD Example Rung FIFO UNLOAD (EN) COUNTER ADDR: FIFO SIZE: NUMBER IN FILE: (FL) FILE: 400- 477 INPUT ADDR: INPUT DATA: 0000 (EM) FIFO LOAD (EN) COUNTER ADDR: FIFO SIZE: NUMBER IN FILE: (FL) FILE: 400- 477...
Page 254 Chapter Bit Shifts 14.0 The Bit Shift instructions are: General Bit Shift Left Bit Shift Right Examine Off Shift Bit Examine On Shift Bit Set Shift Bit Reset Shift Bit The Bit Shift Left and Bit Shift Right instructions are output instructions used to construct and manipulate a synchronous bit shift register from 1 to 999 bits in length.
Page 255 Chapter 14 Bit Shifts Figure 14.1 BIT SHIFT LEFT/RIGHT Operation (A.) 128 Bit Shift Register (Starting at Location 400) Input Bit A 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 16 15 14 13 12 11 10 Bit one of Bit Shift Register Output Bit A...
Page 256 Chapter 14 Bit Shifts Upon false-true transition, bit A from a particular input word will be shifted into the first bit of the bit shift register. Bit 1 will move to the left and displace bit 2. Bit 2 will displace bit 3, etc. Each bit displaces the one to its left until the last bit in the word (bit 16) is reached.
Page 257 Chapter 14 Bit Shifts Figure 14.2 BIT SHIFT LEFT Format BIT SHIFT SHIFT (EN) COUNTER ADDR: NUMBER OF BITS: FILE: 110- 110 INPUT: 010/00 (DN) OUTPUT: 010/00 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 258 Chapter 14 Bit Shifts Figure 14.3 BIT SHIFT LEFT Example Rung BIT SHIFT SHIFT (EN) COUNTER ADDR: NUMBER OF BITS: FILE: 400- 407 INPUT: 130/17 (DN) OUTPUT: 420/00 14.2 The Bit Shift Right output instruction constructs a synchronous bit shift register from 1 to 999 bits in length .
Page 259 Chapter 14 Bit Shifts 14.2.1 Programming Bit Shift Right Instruction WARNING: The counter address specified for the Bit Shift Right instruction should be reserved for that instruction. Do not manipulate the counter preset or accumulated values. Inadvertent change to these values could result in hazardous or unpredictable machine operation or a run-time error.
Page 260 Chapter 14 Bit Shifts Figure 14.4 EXAMINE OFF SHIFT BIT Format EXAMINE OFF SHIFT BIT FILE: BIT NO.: Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 261 Chapter 14 Bit Shifts 14.4 This condition instruction examines a user specified bit in a bit shift register, such as shown in Figure 14.1, for an on or 1 condition. The Examine On Shift Bit instruction can be used alone or in conjunction with other input instructions to affect the rung decision.
Page 262 Chapter 14 Bit Shifts Figure 14.7 EXAMINE ON SHIFT BIT Example Rung EXAMINE ON SHIFT BIT FILE: BIT NO.: 14.5 The Set Shift Bit output instruction sets a specified bit in a bit shift register such as that shown in Figure 14.8. The user specifies the bit number of the Set Shift Bit bit to be set and the starting address of the file.
Page 263 Chapter 14 Bit Shifts Figure 14.8 SET SHIFT BIT Format SET SHIFT BIT FILE: BIT NO.: Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 264 Chapter 14 Bit Shifts Instruction overview: Output instruction 3 words of users program required Key sequence: [SHIFT REG] 17 14.6.1 To program a Reset Shift Bit instruction press [SHIFT REG] 17. A display represented by Figure 14.10 will appear. Programming Reset Shift Bit Instruction Figure 14.10 RESET SHIFT BIT Format...
Page 265 Chapter Sequencer Instructions 15.0 Sequencer Instructions are powerful block instructions. They operate on up to 4 words (64 bits) at a time. There are three sequence instructions: General Sequencer Output, Sequencer Input and Sequencer Load. Sequencer instructions can be used to transfer information from the data table to output word addresses for the control of sequential machine operation (Sequencer Output);...
Page 266 Chapter 15 Sequencer Instructions Sequencer instructions, when enabled, increment to the next step and then the operation is performed. Figure 15.1 Sequencer Table Step Word 1 Word 2 Word 3 Word 4 00110101 11000101 00011101 11001010 10111011 11001011 01011101 01011111 01110100 00011101 00010111 00110011 "...
Page 267 Chapter 15 Sequencer Instructions 15.1 The Sequencer Output instruction functions in a manner analogous to a mechanical drum sequencer. Sequencer Output Instruction 15.1.1 Consider a music box mechanism containing a cylinder with rows of pegs. As the cylinder turns, the pegs produce tones (output) as they strike the Sequencer Output Analogy spring resonators.
Page 268 Chapter 15 Sequencer Instructions Figure 15.3 Sequencer Output Analogy Peg Locations Step Drum Rotation Cylinder Bit Locations Step Equivalent Sequencer Table 15.1.2 When the rung containing the Sequencer Output instruction goes from false to true, the counter increments to the next step in the sequencer Operation of the Sequencer table.
Page 269 Chapter 15 Sequencer Instructions NOTE: When the rung is false, data is not transferred by the instruction and outputs remain in their last state unless changed by instructions elsewhere in the user program. 15.1.3 A mask is a means of selectively screening out data. The purpose of the mask in the Sequencer Output instruction is to allow unused bits of output Masking Output Data words specified in the instruction to be used for other purposes.
Page 270 Chapter 15 Sequencer Instructions Figure 15.4 Masking Transferred Data Sequencer Word Mask Word Output Word prior to Sequencer Operations Output Word after Sequencer Operations 15.1.4 Instruction Overview Output instruction Key sequence [SEQ] 0 Order of operation is increment then transfer Counter is indexed by the instruction Unused bits in output words can be masked out requires 5-8 words of user program, depending on the number of output...
Page 271 Chapter 15 Sequencer Instructions Figure 15.5 SEQUENCER OUTPUT Format SEQUENCER OUTPUT (EN) COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: (DN) FILE: 110- 110 MASK: 010- 010 OUTPUT WORDS Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed (3 or 4) will depend on the size of the data table.
Page 272 Chapter 15 Sequencer Instructions Figure 15.6 SEQUENCER OUTPUT Example Rung SEQUENCER OUTPUT (EN) COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: (DN) FILE: 600- 621 MASK: 211- 212 OUTPUT WORDS When switch 114/14 closes, the Sequencer Output instruction increments to step 008 and controls the 32 outputs corresponding to the specified output words (less those output that are masked).
Page 273 Chapter 15 Sequencer Instructions the data monitor display of a sequencer instruction and a file instruction should be noted. The Sequencer Output instruction will be used as an example. Each column in the sequencer table represents the data for each output word.
Page 274 Chapter 15 Sequencer Instructions 15.2 The Sequencer Input instruction is a rung-conditioning instruction. It compares machine input and other input data with data stored in the Sequencer Input Instruction data table for equality. It can be used alone or in a series and/or parallel combination with other rung-condition instructions to determine the status of an output.
Page 275 Chapter 15 Sequencer Instructions 15.2.4 Programming the Sequencer Input Instruction WARNING: The counter address for the Sequencer Input instruction should be reserved for the instruction and the instruction(s) which manipulate the accumulated value. Do not inadvertently manipulate the preset or the accumulated values. Inadvertent changes to these values could result in unpredictable of hazardous machine operation or a run-time error.
Page 276 Chapter 15 Sequencer Instructions An example rung containing the Sequence Input instruction is shown in Figure 15.10. The following parameters have been entered into the instruction: Counter Address – 0055 Current Step – 006 Sequencer Length – 014 Words per Step – 4 File –...
Page 277 Chapter 15 Sequencer Instructions 15.3 The Sequencer Load instruction is an output instruction. It is used to load data into table locations such as files or sequencer tables. Sequencer Load Instruction 15.3.1 The Sequencer Load instruction receives data from up to 4 independent data table word address(es) specified in the instruction.
Page 278 Chapter 15 Sequencer Instructions 15.3.2 Instruction Overview Output Instruction Key sequence [SEQ] 2 Order of operation is increment then load Counter is indexed by the instruction Instruction does not utilize a mask Requires 4–7 words of user program depending on the number of load words used.
Page 279 Chapter 15 Sequencer Instructions Figure 15.11 SEQUENCER LOAD Format SEQUENCER LOAD (EN) COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: (DN) FILE: 110- 110 INPUT WORDS Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 280 Chapter 15 Sequencer Instructions Figure 15.12 SEQUENCER LOAD Example Rung 0056 SEQUENCER LOAD (EN) COUNTER ADDR: 0056 CURRENT STEP: 0056 SEQ LENGTH: WORDS PER STEP: (DN) FILE: 0510- 0567 INPUT WORDS 0111 0113 0112 0314 15 16 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 281: File Logic Instructions 16
Chapter File Logic Instructions 16.0 This section assumes the reader has Chapter 12, Data Transfer File Instructions, and is familiar with the concepts and terms introduced in that General section. 16.1 The File-to-File logic instructions are: File to File Logic File-to-File AND Instructions File-to-File OR...
Page 282 Chapter 16 File Logic Instructions 16.1.1 This output instruction operates on the contents of two data files A and B and places the result of the operation AND in a third File R. File to File AND The logic operation AND compares each bit in File A to the corresponding bit in File B.
Page 283 Chapter 16 File Logic Instructions Figure 16.2 FILE TO FILE AND Format FILE TO FILE AND (EN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110- 110 (DN) FILE B: 110- 110 FILE R: 110- 110 RATE PER SCAN: Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 284 Chapter 16 File Logic Instructions Figure 16.3 FILE TO FILE AND Example Rung FILE TO FILE AND (EN) COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 410- 415 (DN) FILE B: 574- 601 FILE R: 610- 615 RATE PER SCAN: 16.1.2 This output instruction operates on the contents of data Files A and B and places the result of the operation OR in File R (Figure 16.1).
Page 285 Chapter 16 File Logic Instructions Programming of File to File OR Instruction WARNING: The counter address for the File-to-File OR instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or run-time error.
Page 286 Chapter 16 File Logic Instructions Instruction Overview: Output instruction Key Sequence [FILE] 18 Requires six words of user program Can operate in incremental, distributed complete or complete mode Counter is internally indexed by the instruction Programming File to File XOR Instruction WARNING: The counter address for the File-to-File XOR instruction should be reserved for that instruction.
Page 287 Chapter 16 File Logic Instructions Programming File Complement Instruction WARNING: The counter address for the File-to-File Complement instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could in unpredictable or hazardous machine operation or a run-time error.
Page 288 Chapter 16 File Logic Instructions Figure 16.5 shows the format of Figure 16.4 after values for the following condition have been entered: COUNTER ADDR – word 050 POSITION – 003 FILE LENGTH – 006 FILE A – 474-501 FILE R – 410-415 RATE PER SCAN –...
Page 289 Chapter 16 File Logic Instructions Figure 16.6 WORD TO FILE LOGIC Operations Operation AND, OR, XOR File B File R Data Table Word Position File Length In this diagram, a logic operation is being performed on the word and step three of File B and the result stored in step three of File R. 16.2.1 This instruction performs an AND operation on the contents of a specified word in the data table and a word from File B.
Page 290 Chapter 16 File Logic Instructions Counter is not modified by instruction. Needs to be externally indexed by user program. Programming Word to File AND Instruction WARNING: The counter address for the Word-to-File AND instruction should be reserved for the instruction and the instruction(s) which manipulate the accumulated value.
Page 291 Chapter 16 File Logic Instructions Figure 16.8 shows the format of Figure 16.7 after data has been entered for the following conditions: COUNTER ADDR – Word 200 POSITION (set by program) – 003 FILE LENGTH – Each file has 6 steps WORD ADDR –...
Page 292 Chapter 16 File Logic Instructions Table 16.E Truth Table for Logical WORD TO FILE OR Corresponding Bit In File B File R Bit In Word Instruction Overview: Key sequence: [FILE] 17 Output instructions Requires 5 words of user program Counter is not modified by instruction. Needs to be externally indexed by user program.
Page 293 Chapter 16 File Logic Instructions (Figure 16.6). If the bits are both 1 or 0, a 0 is stored in the corresponding bit of File R. For other conditions, a 1 is stored in File R (Table 16.F). Table 16.F Truth Table for Logical WORD TO FILE XOR Corresponding Bit In File B...
Page 294 Chapter File Search and File Diagnostic Instructions 17.0 The File Search instruction locates all words in a file whose data is identical to a specific input word’s data. General The File Diagnostic instruction can be used to locate discrepancies between actual and desired states of I/O’s by searching for 1 in the result file of an XOR operation (Section 16.1.3).
Page 295 Chapter 17 File Search and File Diagnostic Instructions The process continues until the end of the file is reached (position = file length), at which time the done bit is set. The next false-true transition starts the search again at the beginning of the file. If the last word of the file contains a match, the position will equal file length, but the done bit will not be set.
Page 296 Chapter 17 File Search and File Diagnostic Instructions Figure 17.2 FILE SEARCH Format FILE SEARCH (EN) COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDR: (DN) FILE: 110- 110 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Page 297 Chapter 17 File Search and File Diagnostic Instructions Figure 17.3 FILE SEARCH Example Rung FILE SEARCH (EN) COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDR: (DN) FILE: 400- 477 17.2 The File Diagnostic instruction can be used for programmed machine diagnostic error detection in conjunction with File-to-File XOR or File Diagnostics Word-to-File XOR instructions.
Page 298 Chapter 17 File Search and File Diagnostic Instructions Figure 17.4 FILE DIAGNOSTIC (A.) XOR Instruction Set Up File A File B File R Result Stored in File R Actual Desired A 1 in File R indicates an I/O States I/O States error in machine operation.
Page 299 Chapter 17 File Search and File Diagnostic Instructions Programming File Diagnostic Instruction WARNING: The counter address specified for the File Diagnostic instruction should be reserved for that instruction. Do not manipulate the counter preset or accumulated values. Inadvertent change to these values could result in hazardous or unpredictable machine operation or a run-time error.
Page 300 Chapter 17 File Search and File Diagnostic Instructions COUNTER ADDR – 200 FILE LENGTH – 006 FILE – First word is 320, last word is 325 BASE – First word is 012, last word is 017 ERROR – Error number and location will be stored in words 500 to 502 inclusive The procedure for using the data monitor for data entry or monitor is presented in Chapter 12.
Page 301 Chapter Troubleshooting Aids 18.0 The following troubleshooting aids are useful during starting-up and when troubleshooting a system: General Bit manipulation and monitor functions Force on and force off functions Forced addressed display Temporary end instruction ERR message display The troubleshooting aids are summarized in Table 18.A. Table 18.A Troubleshooting Aids Function...
Page 302 Chapter 18 Troubleshooting Aids Function Mode Key Sequence Description Removing a FORCE OFF Test or Run/Program [FORCE OFF] [REMOVE] Position the cursor on the Image Table bit or bit instruction whose force OFF is to be removed and press the key sequence.
Page 303 Chapter 18 Troubleshooting Aids 18.1.2 Bit monitor can function when the processor is in any mode. By pressing the key sequence [SEARCH] 53 [Key Sequence of Word Address], the Bit Monitor status of all 16 bits of the desired word will be displayed. While the cursor is in the word address field, the [1] and [0] keys can be used to change address digits.
Page 304 Chapter 18 Troubleshooting Aids All force on or all force off functions can be removed at once in ladder diagram display by breaking communications between the T3 industrial terminal and the processor or by pressing either of the following sequences: [FORCE ON] [CLEAR MEMORY] [FORCE OFF] [CLEAR MEMORY] The on or off status of a forced bit will appear beneath the bit instruction in...
Page 305 Chapter 18 Troubleshooting Aids 18.4 The Temporary End instruction can be used to test or debug a program up to the point where it is inserted. It acts as a program boundary because Temporary End Instruction instructions below it in user program are not scanned or operated upon. Instead, the processor immediately scans the I/O image table followed by user program from the first instruction to the Temporary End instruction.
Page 306 Chapter 18 Troubleshooting Aids Section 1.2.3, Industrial Terminal Compatibility.) Those ERR messages do not contain the 4-digit hex value and do not cause a processor fault. If an illegal OP code should occur, the rung containing it can be compared with the equivalent rung in a hard copy printout of the program.
Page 307 Chapter Special Programming Techniques 19.0 There are several programming techniques that offer versatile control of the process of machine operation. They include: General One-Shot 19.1 The one-shot programming technique uses a scan counter to set a bit on for one scan only. There are two types of one-shots that can be programmed. One Shot Leading Edge Trailing Edge...
Page 308 Chapter 19 Special Programming Techniques When bit 112/04 makes a false-true transition, the scan counter begins to increment once each scan. When the accumulated value of the scan counter is equal to 001, bit 203/00 (the one-shot bit) will be on. The next scan, if bit 112/04 is off, the scan counter will be reset to 000.
Page 309: Addressing
NOTE: The illustrations show a PLC-2 family processor in the first slot of the 1771 I/O chassis. In a PLC-2/30 system this is replaced with an adapter module. You must properly address your hardware so that it relates to your ladder diagram program.
Page 310 Appendix A Addressing Figure A.1 Hardware/Data Table Addressing Relationships Concept Example Hardware Terminology Hardware Terminology Input (1) or Output (0) Output: 0 Rack No. (1 7) Rack No.: 1 I/O Group No. I/O Group No.: 0 (0 7) Terminal No. Terminal No.: 12 (00 07, 10 17) Word...
Page 311 Appendix A Addressing A.2.1 The processor addresses two I/O module slots as one I/O group. 2 Slot Addressing Each physical 2-slot I/O group is represented by a word in the input image table and a word in the output image table. Each input terminal corresponds to a bit in the input image table word and each output terminal corresponds to a bit in the output image table word.
Page 312 Appendix A Addressing Figure A.2 Illustration of 2 slot Addressing with Two 8 point Input Modules 2 slot I/O Group NOTE: Two 8 point input modules use one full word of the input image table. Input Input Terminals Terminals Output image table word corresponding to the I/O group.
Page 313 Appendix A Addressing Using 8 Point I/O Modules Figure A.3 Illustration of 2 slot Addressing with 8 point Input and Output Modules I/O Module Group Input Output Terminals Terminals Output image table word corresponding to the I/O group. 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Used Output bits Unused Output bits Input image table word corresponding...
Page 314 Appendix A Addressing Using 16 Point I/O Modules High-Density (16-point) I/O modules provide 16 input terminals or 16 output terminals. 16-point I/O modules use a full word in the input or output image table. Two 16-point modules (one input and one output) can be used in a 2-slot I/O group (Figure A.4).
Page 315 Appendix A Addressing that performs the opposite (complementary) function; an input module complements an output module and vice-versa. You can use an 8-point module with 16-point module in a 2-slot group; however, it too must perform the opposite function. In this arrangement, eight bits in the I/O image table are unused.
Page 316 Appendix A Addressing A.2.2 The processor (by way of the adapter) addresses one I/O module slot as one I/O group. 1 Slot Addressing Each 1-slot I/O group is represented by a word in the input image table and a word in the output image table. You have 16 input bits and 16 output bits available for each slot.
Page 317 Appendix A Addressing Figure A.6 Illustration of 1 slot Addressing with 16 point I/O Modules 1 slot 1 slot I/O Group I/O Group Input Output Terminals Terminals Output image table word Output image table word corresponding to the I/O group. corresponding to the I/O group.
Page 318 Appendix A Addressing Figure A.7 Assigning I/O Rack Numbers with 1 slot Addressing Assigned Assigned I/O Group No. I/O rack number 1 I/O rack number 2 Í Í Í Earlier (Figure A.1), we showed how the 5-digit input or output instruction is associated with a particular I/O module terminal.
Page 319 Appendix A Addressing Figure A.8 Example of 1 slot Addressing I/O Group No. Rack 1 Rack 2 Í Í Í I/O Group 1 I/O Group 1 Address Address 1 1 1 Input Rack I/O Group NOTE: When addressing a block transfer module, it must be addressed by the lowest group number that it occupies and at slot 0.
Page 320 Appendix A Addressing You select 1/2-slot addressing by setting two switches in the I/O chassis backplane switch assembly. See your scanner’s or adapter’s users’ manual for the specific switches and their settings. Figure A.9 illustrates the 1/2-slot addressing concept with a 32-point I/O module.
Page 321 Appendix A Addressing Figure A.9 Illustration of 1/3 slot Addressing Using a 32 point I/O Module 32-point Input Module Bit # Bit # Input Word 0 1/2-slot 10 7 1/2-slot I/O Group I/O Group Image Table Words Allocated Outut Word 0 for I/O Group 0 10 7 Unused...
Page 322 Appendix A Addressing Assigning I/O Rack Numbers When you select 1/2-slot addressing, each slot corresponds to two I/O groups. You still assign one rack number to eight groups; however, with 1/2-slot addressing this requires only four slots. Thus, in a single 16 slot chassis, you now can have four I/O racks (Figure A.10).
Page 323 Appendix A Addressing Figure A.11 illustrates addressing 4 modules, each with the same I/O group number, but in four different racks of a single I/O chassis. (This method is explained in Figure A.11.) Figure A.11 Group Address of a Module in Four Different Racks I/O Group No.
Page 324 Its addressing modes are dependent upon what it is addressing (local or System Configurations remote I/O) and how it is communicating with its I/O modules. If you have a PLC-2/30 communicating with a local I/O chassis through a 1771-AL Local I/O Adapter module, you can only use 2-slot addressing.
Page 325 Appendix A Addressing Table A.A Series B, 1771 Universal I/O Chassis, Addressing Modes vs. I/O Adapters Addressing Mode 2 slot 1 slot 1/2 slot I/O Adapter Cat. No. I/O Points Per Module 1771 AL 1771 AS 1771 ASB Series A 1771 ASB Series B Legend:...
Page 326 Appendix Number Systems There are four numbering systems used with programmable controllers. They are: General Decimal Octal Binary Hexadecimal These numbering systems differ by their number sets and place values. The decimal numbering system uses a number set made up of ten digits: the numbers 0 through 9.
Page 327 Appendix B Number Systems The octal numbering system is used to address word and bit locations in the data table. Its number set is composed of eight digits: the numbers 0 Octal Numbering System through 7. Just like all numbering systems, each digit in an otcal number has a certain place value, represented by a power of eight (Figure B.2).
Page 328 Appendix B Number Systems The binary numbering system uses a number set that consists of two digits: the numbers 0 and 1. All information in memory is stored as an Binary Numbering System arrangement of 1 and 0. Each digit in a binary number has a certain place value expressed as a power of two (Figure B.3).
Page 329 Appendix B Number Systems B.3.1 Binary coded decimal (BCD) uses an arrangement of 12 binary digits to represent a 3-digit decimal number from 000 to 999 (Figure B.4). Each Binary Coded Decimal group of 4 binary digits is used to represent a decimal number from 0 to 9. The place values for each group of 4 digits are 20, 21, 22 and 23 (Table B.A).
Page 330 Appendix B Number Systems Table B.A BCD Representation Place Value Decimal Equivalent The decimal equivalent for a group of 4 binary digits is determined by multiplying the binary digit by its corresponding place value and adding these numbers. B.3.2 Binary coded octal (BCO) uses an arrangement of 8 bits (one byte) to represent a 3-digit octal number from 000 to 377 (Figure B.5).
Page 331 Appendix B Number Systems Table B.B Octal Representation Place Value Octal Equivalent The hexadecimal numbering system has a number set of 16 digits: the numbers 0-9 and the letters A-F (Table B.C). The letters A-F represent the Hexadecimal Numbering decimal numbers 10-15 respectively. System Table B.C Numbering System Conversion Chart...
Page 332 Appendix B Number Systems Figure B.6 Hexadecimal to Decimal Conversion 0 x 16 1 x 16 = 256 10 x 16 = 160 7 x 16 01A7 = 423 Because each hexadecimal digit represents 4 binary digits, it is easy to convert a hexadecimal number to a binary number.
Page 333 Appendix Programming .01 Second Timers The bulletin 1772 Mini-PLC-2 Programmable Controller permits you to enter On Delay Timer (TON), Off Delay Timer (TOF), and Retentive Introduction Timer (RTO) instructions with a 0.01-second time base. These are also referred to as 10-millisecond (10-msec) timers. Timers with a 10-msec time base provide you with greater timing resolution and accuracy than is possible with a 0.1-second time base.
Page 334 Appendix C Given any preset value, a Mini-PLC-2 controller timer is accurate to within one interval of its time base (and this is generally true for any type of Timer Accuracy timer). Specifically, the timed interval does not exceed the preset interval, but it may be as much as 1 time-base unit shorter than the preset.
Page 335 Appendix C Figure C.1 Timing Diagram Note, too, that these timing accuracies refer only to internal Mini-Processor operation. That is, these intervals refer to the length of time which occurs between the moment that a timer is initialized (bit 17 set) and the moment that the timed interval is complete (bit 15 set).
Page 336 Appendix C In general, 10-msec timers are used for these functions: 10 Msec Timers - Typical monitor events on a high-speed assembly or transfer line, such as that Applications used in canning and bottling machines generate short-duration pulses for accurate positioning control. For example, on a bottling or canning line, photoelectric sensors or electromagnetic proximity switches can be used to detect the movement of bottles/cans.
Page 337 For selection of suitable I/O modules, contact your local Allen-Bradley representative for further assistance. The remainder of this Appendix discusses programming techniques which you must use to effectively program 10-msec timers. The required...
Page 338 Appendix C C.5.1 The Mini-PLC-2 Processor performs an I/O scan and then a program scan, in sequence. Scan time is the sum of the times required for both of these Scan Time scans. (Note that the processor does not scan unused memory, nor does it scan that portion of the memory used to store messages.) During an I/O scan, the processor examines Output Image table bits updates or corrects the ON/OFF signals applied to the output modules.
Page 339 Appendix C The processor can also update a timer only at the instant it is executing that timer instruction. Remember that an integral timing clock (see the preceding section, Timer Accuracy, on the previous page) puts out pulses for the 1.0-, 0.1- and 0.01-second timers. When the 1.0- and 0.1-second timers are used in a program, the timing pulses are always longer than the process or scan time.
Page 340 Appendix C Figure C.2 Typical Timing Diagram for 0.01 Second Timer These multiple entries of the 0.01-second timer rung will help assure that the accuracy of the timer accumulated value is within the accuracy limits discussed above. Additional programming techniques can help to assure that output devices controlled by the timer are energized or de-energized after as precise a time delay as possible.
Page 341 Appendix C Figure C.3 Typical 0.01 Second Timer Programming In Rungs 2, 3, and 4, Output Energize instructions conditioned by timer bits should also be repeated in the program. When used near the beginning or middle of the program, the Immediate Output instruction addressed to output image table word 014 will help to assure that the output modules respond quickly to timer cycling.
Page 342 Appendix C Assume the processor is using a 128-word data table and has 1,024 words of memory. If all memory words are used, the program will contain 896 instructions. A program of this size might typically have the following distribution: 546 instructions x 18 µsec = 9.8 ms 306 instructions x 28 µsec =...
Page 343 Index Numbers block length, 10 17 block transfer, 10 1 1 slot addressing, basic operation, 10 1 1/2 slot addressing, A 11 block transfer instructions, 10 4 10 msec timers branch instructions, programming techniques, buffering data, 10 12 typical applications, 1771 P2 auxiliary power supply, 2 10 1771 P3, P4, and P5 slot power supplies,...
Page 344 Index I–2 dependent programming, 7 12 digital cassette recorder, get byte - put instruction, displaying and locating errors, get byte and limit test instructions, divide instruction, 6 14 get instruction, down counter instruction, 5 12 dumping memory content onto data cartridge tape, dumping memory content to cassette tape, hardware addressing modes,...
Page 345 Index I–3 ladder diagram logic, operating instructions, 4 14 last state switch, operation, 10 14 leading edge one shot, 19 1 operation of the sequencer input instruction, 15 10 les and equ instructions, operation of the sequencer load instruction, loading memory from a data cartridge tape, 15 13 operation of the sequencer output loading memory from cassette tape,...
Page 346 Index I–4 shift file down instruction, 13 5 special programming techniques, 19 1 shift file up instruction, 13 3 subroutine area, 11 10 special techniques, 19 1 subroutine programming considerations, timer and counter instructions, 5 14 11 12 word to file move instructions, 12 19 subtract instruction, 6 13...
Page 347 As a subsidiary of Rockwell International, one of the world’s largest technology companies — Allen-Bradley meets today’s challenges of industrial automation with over 85 years of practical plant-floor experience. More than 13,000 employees throughout the world design, manufacture and apply a wide range of control and automation products and supporting services to help our customers continuously improve quality, productivity and time to market.
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Allen-Bradley PLC-2/30 Programming And Operations Manual

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Summary of Contents for Allen-Bradley PLC-2/30

Page 5: Introduction 1

Page 18: Hardware Considerations 2

Page 45: Report Generation 9

Page 281: File Logic Instructions 16

Page 309: Addressing

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