Philips TC7.1U CA Service Manual page 37

Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.2.7 IM101
This is a cost-effective ATSC DTV processor targeted for low-
cost, high-volume ATSC DTV receivers and converter boxes
that convert DTV signals to NTSC/PAL output for viewing on
legacy TV receivers.
Block diagram is as follows:
Figure 9-7 Blockdiagram ATSC processor IM101
It is a System on Chip (SoC) device that integrates the main
function of a DTV receiver. A Transport Packet Parser (TPP) is
integrated that includes POD to Host interface support for
Digital Cable. The MP HL MPEG-2 Video Decoder is capable
of fully decoding all ATSC DTV video formats.
A Display Processor is included with the ability to convert any
ATSC DTV format to any other format, including non-standard
display resolutions support for panel based DTVs.
Multi-Format Audio decode and processing is supported with
the Audio Processor.
The On Screen Display (OSD) controller and 2D Graphics
Accelerator can support applications with sophisticated
Graphic User Interface.
An ARM926 CPU is included, which controls the memory
mapped internal devices and runs the application software.
9.2.8 II101
It offers a high level of integration that greatly simplifies
unidirectional digital cable ready receiver design. For the main
digital channel (Forward Application Transport - FAT), the
THEATER 314 integrates the QAM demodulator and FEC
decoder. In addition, it integrates part of the IF circuitry (one
SAW filter and one amplifier) typically required for the interface
between the tuner and the digital demodulator.
Block diagram is as follows:
Figure 9-8 Blockdiagram II101
9.2.9 IM201
The EDD1216AATA is a 128 Mbits Double Data Rate (DDR)
SDRAM organized as 2,097,154 words 16 bits 4 banks. Read
and write operations are performed at the cross points of the
CK and the /CK. This high speed data transfer is realized by the
2 bits pre-fetch pipelined architecture.
Data strobe (DQS) both for read and write are available for high
speed and reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 66-pin plastic TSOP (II).
9.2.10 IM102
It is a 16 Mbit, 3.0 Volt-only Flash memory organized as
2,097,152 bytes or 1,048,576 words. The device is offered in
48-ball FBGA, and 48-pin TSOP packages. The word-wide
data (x16) appears on DQ15-DQ0; the byte-wide (x8) data
appears on DQ7-DQ0. This device is designed to be
programmed in-system with the standard system 3.0 volt VCC
supply. A 12.0 V VPP or 5.0 VCC are not required for write or
H_17090_048.eps
erase operations. The device can also be programmed in
290307
standard EPROM programmers.
Block diagram is as follows:
H_17090_049.eps
290307
TC7.1U CA
Figure 9-9 Blockdiagram IM102
9. EN 37
H_17090_058.eps
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