Table of Contents
Advertisement
TYPE 1391-B PULSE, SWEEP, AND TIME-DELAY GENERATOR
exponential voltage produced by the charging of a capacitor
through i t s associated resistor toward the supply voltage. The
slope i s correctly s e t for the selected range by a potentiometer,
for all ranges except one. R232 provides an adjustable s t e p of
initial plate voltage on the 1-sec range to compensate for the
lower starting plate voltage due to the five-megohm charging re-
sistor on this range. R283 provides a s t e p to speed up the be-
ginning of the 1-10-psec range to overcome the effects of stray
capacitance, while on the same range C222 provides an adjust-
ment to permit exact duplication of capacitance in the presence
of strays for each instrument. The rising exponential voltage pro-
duced by the switching action of V203 is coupled by a cathode
follower (V204A) to the grid (pin 2) of V205A, the delay ampli-
tude comparator.
4.3.4 DELAY AMPLITUDE COMPARATOR. V205 is a Schmitt
amplitude-comparison circuit. A d-c reference voltage, estab-
lished by the DELAY MICROSECONDS control, is used to trans-
late i t s triggering d-c level from a minimum of about 15 volts
over a hundred-volt span. When the DELAY MICROSECONDS
control
is
set a t mimimum, the sweep must r i s e only about 10
volts before the amplitude comparator triggers; however, with
the control at maximum, the voltage must rise to over 100 volts.
The minimum and maximum voltages are s e t by R236 and R238
to give the correct delay readings on the 10-psec-100-psec
range. Obviously, if the delay sweep were linear and if the vol-
tage established by the DELAY MICROSECONDS control were
linear a s a function of angle, the DELAY dial reading would be
linear. It i s apparent that the delaying sweep i s not linear, being
one third of a complete exponential change curve a t i t s maximum
value. Due to the current drawn by V205 and R219 from the arm
of the delay potentiometer R237, the change in voltage with
angle
is
nonlinear and closely matches the exponential, result-
ing in a linear delay scale.
4.3.5 DELAY RESET TRIGGER STAGE. After thelapse oftime
determined by the sweep and the amplitude-comparison reference
voltage, V205 triggers, the left side goes on and the right side
goes off. The regenerative rise in voltage a t the right-hand plate
of V205 causes V204B, the reset trigger amplifier, to conduct,
producing a negative trigger, which i s fed to the grid of V202,
turning V202 off and terminating the sweep. T h i s reset pulse i s
also fed through C234 to start the coincidence gate. The mono-
stable character of the main delay loop should now be apparent.
If, for some reason, the delay reset trigger produced by the am-
plitude comparator fails to reach and reset the gate, no second
trigger can be produced by the amplitude comparator, and the
sweep voltage will rise to a maximum value s e t by the grid cur-
rent in V204A. The loop will be quiescent in this "locked outn
position. The action of the circuit can then be initiated only by
artificial reset trigger injected at the grid of V202. This is done
by means of the RESET switch, S202, which momentarily removes
the bias from V204B, producing the negative pulse to restore
the loop to i t s normal state. The circumstances under which the
"lock out" conditions usually occur are:
a. upon warmup, if V202 comes on first. (This can be per-
manently remedied by reversal of V201 and V202.)
b. when the delay circuit
is
used a s a frequency divider
and/or when the delay control is s e t to produce a delay nearly
equal to the input period.
4.4 COINCIDENCE CIRCUITS.
4.4.1 GENERAL. The 3-1000-psec monostable gate is opened
by the negative delay reset trigger. In normal operation the posi-
tive early transition of this gate turns on the coincidence ampli-
fier.
The pulse of plate current of the coincidence amplifier i s
inverted by T201 to drive the delay trigger generator stage into
conduction. The delay trigger generator develops the delayed
trigger in an inductor-diode pulse-forming network in i t s plate.
T h i s circuit, the following pulse amplifier, and cathode follower
are identical in design to the equivalent circuits of the input
system explained in paragraph 4.2. The delayed trigger i s fed to
one side of the SWEEP TRIGGER switch (S203), and the direct
trigger to the other. Operation of this switch c a u s e s the sweep
to be started by either the delayed or the direct trigger.
When the coincidence system i s to beused for time selec-
tion a s described in paragraph 1.3.3, the sum of the 3-1000-psec
gate from V206 and an input pulse from J201 (POS) or J205
(NEG) is required to turn the coincidence amplifier stage
on. The coincidence amplifier bias i s increased a s the COIN-
CIDENCE SENSITIVITY control (R256) i s turned counterclock-
wise. The 3-1000-psec gate alone can not switch V207A into
conduction when the sensitivity i s reduced. The combination of
the gate and positive pulses at the junction of R289 and R290
will switch V207A on and produce the delayed synchronizing
signal.
4.4.2 COINCIDENCE GATE CIRCUIT. The right-hand side of
the 3-1000-psec monostable gate, V206B, i s normally conduct-
ing with i t s cathode near -80 volts and i t s grid slightly positive
with respect to cathode. The plate current of this tube, flowing
through R256, R257, and R249 to ground, produces a bias vol-
tage, which normally keeps the left-hand side of V206A off.
With this tube off, i t s cathode i s slightly negative with respect
to ground because of the forward drop of D205. The negative de-
lay reset trigger starts the regenerative action of the monostable
gate, during which the right-hand side of V206B goes off, turn-
ing the left-hand side on. After switching, the grid of the left-
hand side is a t ground potential and i t s cathode i s slightly posi-
tive with respect to ground; thus D205 i s a high resistance, and
R251 is a feedback resistor, which stabilizes the plate durrent
of V206-left. The "offn time of V206-left depends on i t s plate
'
swing and the r-c time constant controlled primarily by C235,
R254, and R255. The "off" time of V206-right i s controlled a s
R253 varies the plate swing. C253 and R288 alter the initial
shape of the timing grid waveform for V2OG-right to permit smooth
timing down to
3
microseconds. When the timing r-c combination
h a s discharged enough for the right-hand tube again to go into
conduction, i t s plate voltage begins to fall, lowering the grid
voltage on the right-hand side, and the circuit regenerates and
returns to i t s original stable state, terminating the gate. The
gate is directly coupled to the grid of the coincidence amplifier
through R289. The resistive adder i s compensated by C254.
4.4.3 COINCIDENCE AMPLIFIER. When the 3-1000-psec gate
is off, grid 2 of V207Ais about -10 volts; while i t is on, the grid
is near ground potential. R265 in the cathode of V207A is the
COINCIDENCE SENSITIVITY control, producing from 3 to 33
volts of additional bias for this stage. In the NORMAL position,
the 3 volts of bias alone will not hold the stage in cutoff when
Advertisement
Table of Contents
