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GENERAL RADIO COMPANY
Section
4
DETAILED CIRCUIT DESCRIPTIONS
4.1
GENERAL.
The following circuit descriptions are presented
in much the same order a s that taken by a signal, beginning with
the input circuits. For convenience in maintenance, the compo-
nents in each circuit group are numbered in the same series, a s
shown in the following list:
Tubes and
Circuit
Components No. Schematic Diagram
Input Circuits
100's
Figure 5.1
Delay Circuits
200's
Figure 5.2
Sweep Circuits
300's
Figure 5.3
Pulse-Timing Circuits
400's
Figure 5.4
Pulse-Generating Circuits
500's
Figure 5.5
Power Supply
600's
Figure 5.6
4.2 INPUT CIRCUITS.
(See Figure 5.1.) The trigger circuit con-
sisting of dc amplifier VlOlA and Schmitt circuit V102 produces
the brief direct trigger pulse, and maintains i t s slope and ampli-
tude constant irrespective of the rate of change of input volt-
age a t the PRF DRIVE terminals. The amplifier VlOlA is con-
nected to the P R F DRIVE binding post through blocking capa-
citor ~ l l l and the symmetrical limiter circuit R101, D102, and
D103. For dc operation, C l l l is shorted out by S101. VlOlA
serves a s a d-c amplifier for the Schmitt circuit, V102. If V102A
is in conduction, i t s plate current will maintain the cathode volt-
age for both s i d e s a t about 95 volts. If the plate voltage of VlOlA
is below 90 volts, the circuit is stable and V102A remains in
conduction. Now suppose the plate voltage of VlOlA is increased
until V102B begins to conduct. The decreasing plate voltage of
V102B reduces grid voltage on V102A and therefore reduces the
cathode voltage, making V102B conduct even more heavily. This
positive feedback quickly turns V102A off and V102B on. When
the plate voltage of VlOlA is again reduced to below 95 volts,
V102A i s sufficiently below i t s cutoff voltage s o that the grid
voltage ofV102B must be reduced to below 90 volts before V102
switches back to the original state. Therefore the circuit exhibits
a hysteresis effect.
The bias establishing the quiescent plate current for
VlOlA i s normally s e t in the center of this hysteresis loop. A
positive-going voltage a t the grid of VlOl is amplified and
swings V102B into i t s regenerative region, turning it off and pro-
ducing a positive transition a t i t s plate. The TRIGGER SELEC-
TOR switch is shown in the positive-going position, s o that
this wave front is differentiated by C103 and R112 to a positive
trigger that momentarily switches V103A on.
R103 and R104 control the bias on VIOLA, establishing
the center of the hysteresis loop. An adjustment of R103, the
TRIGGERING LEVEL control, can:
a. permitVl02 to switch on either a small positive or a neg-
ative input pulse. (Note that in the optimum sensitivity adjust-
ment, the a-c component of a brief input pulse may not be ade-
quate to cause the hysteresis loop to be traversed.)
b. optimize the sensitivity of the trigger for small signal in-
puts. (This i s the normal setting.)
c. select an exact voltage a t which V102 will switch, thus
permitting the exact sensing of zero crossing for large signals.
The pentode section of V103 is turned on by the positive trig-
ger generated by the Schmitt circuit on the selected zero cros-
sing, either positive- or negative-going. A network in the plate
of V103A produces the 0.10-psec, 20-volt negative direct trig-
ger. A longer-duration negative trigger of somewhat higher am-
plitude, developed across LlOl and R113, is capacitively
coupled through the 0.2-psec delay line DLlOl to the grid of
V103B. V103B is normally conducting a t zero bias, and, when
turned off by the negative trigger, produces a 100-volt positive
sync, about 1 p s e c in duration, which is fed toV104A, a cathode
follower capacitively coupled to the DIRECT
SYNC
OUT termi-
nals. DLlOl provides a 0.2-psec time delay in the direct sync
channel. The total delay accumulated between the P R F DRIVE
and DIRECT SYNC OUT terminals i s about 0.4 psec. This de-
lay permits the delay and sweep circuits to be precisely cali-
brated a t their minimum values.
4.3 DELAY CIRCUITS.
4.3.1 GENERAL. For convenience, the delay circuits can be
divided into two groups; the main delay circuit, across the top
of Figure 5.2, and the coincidence circuit system, the line of
circuits a t the bottom of Figure 5.2. Idealized waveforms are
shown in the time diagram accompanying the block diagram for
these circuits (Figure 1.4).
The main delay circuit is aloop with a monostablecharac-
teristic. The loop action is started by the direct trigger, which
opens a bistable gate and starts a sweep circuit. When the sweep
voltage eguals the d-c voltage s e t by the TIME DELAY MICRO-
SECONDS control, the amplitude comparator circuit switches,
generating a trigger. The trigger i s amplified and resets the bi-
stable gate, ending the sweep. The loop then remains quiescent
until another direct trigger is received. Since the delay sweep
l a s t s from 1 p s e c (minimum) to one second (maximum), the cir-
cuits up to the amplitude comparator are direct coupled.
4.3.2
DELAY GATE. The delay gate is a bistable circuit. One
gate tube (V201) is normally on, the other (V202) normally off.
t h e supply voltage for the gate is +55 volts and -150 volts with
respect to ground; therefore the plate potential of the conducting
gate tube is negative with respect to ground by about 15 volts.
The gate is opened by the negative direct trigger from the input
circuit, and switches regeneratively to turn V201 off and V202
on. The fall in voltage a t the plate of V202 turns V203 off and
starts the sweep.
4.3.3 DELAY SWEEP GENERATOR. V203 i s normally in con-
duction, with i t s grid slightly positive. Plate load resistors,
ranging from 500 kilohms to five megohms, selected by the DE-
LAY RANGE switch, drop almost the entire power-supply vol-
tage a t the plate ofV203 when i t i s on. When V203 goes off, the
timing capacitor appropriate to the delay range charges through
the selected resistor. Thus the delay sweep is a portion of the
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