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Summary of Contents for Fastrax IT430
- Page 1 REV 1.5 TECHNICAL DESCRIPTION Fastrax IT430 OEM GPS Receiver This document describes the electrical connectivity and main functionality of the Fastrax IT430 OEM GPS Receiver. June 30, 2010 Fastrax Ltd.
- Page 2 Fastrax products are not authorized for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. Fastrax will not warrant the use of its devices in such applications.
- Page 3 2010-06-30 Page 3 of 42 IT430_Tech_doc.doc CHANGE LOG Rev. Notes Date Initial documentation 2010-02-18 Added notes on power up and power removal; relaxed 2010-04-19 operation temperature range between -40ºC and -30ºC; increased module height to 1.85 mm, updated table 3 (added I/O type vs.
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Page 4: Table Of Contents
2010-06-30 Page 4 of 42 IT430_Tech_doc.doc CONTENTS _______________________________________________________________________ GENERAL DESCRIPTION................7 Block diagram..................8 Frequency plan ..................8 SPECIFICATIONS ................... 9 General....................9 Absolute Maximum Ratings ............... 10 OPERATION....................11 Operating modes ................11 Full on mode ..................11 3.2.1 Host port configuration ............. - Page 5 Tape and reel ..................29 REFERENCE DESIGN................... 30 Reference circuit diagram..............30 PCB layout issues ................31 IT430 APPLICATION BOARD ............... 33 Card Terminal I/O-connector ............. 33 Bill of materials .................. 35 Circuit drawing ................... 38 Assembly drawing, Top side.............. 39 Artwork, layer 1 (Top).................
- Page 6 2010-06-30 Page 6 of 42 IT430_Tech_doc.doc COMPLEMENTARY READING The following reference documents are complementary reading for this document: Ref. # File name Document name SiRFstarIV Brochure.pdf SiRFstar IV Brochure CS-129435-MA-N.pdf NMEA Protocol Reference Manual CS-129291-DC-2.pdf Socket Protocol (OSP) Interface Control Document Reflow_soldering_ profile.pdf Soldering Profile...
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Page 7: General Description
IT430_Tech_doc.doc GENERAL DESCRIPTION The Fastrax IT430 is an OEM GPS receiver module, which provides the SiRFstar IV receiver (ref I) functionality using the state of the art SiRF GSD4e chip (ROM variant). The module has ultra small form factor 9.6x9.6 mm, height is 1.85 mm nominal (2.15 mm max). The Fastrax IT430 receiver provides low power and very fast TTFF together with weak signal acquisition and tracking capability to meet even the most stringent performance expectations. -
Page 8: Block Diagram
Block diagram Figure 1 Block diagram Frequency plan Clock frequencies generated internally at the Fastrax IT430 receiver: • 32768 Hz real time clock (RTC) • 8 MHz switched mode regulator (when enabled by command) • 16.369 MHz master clock (TCXO or crystal) -
Page 9: Specifications
2010-06-30 Page 9 of 42 IT430_Tech_doc.doc SPECIFICATIONS General General Specifications Table 1 Receiver GPS L1 C/A-code, SPS Chip set & Tracking sensitivity SiRF IV, GSD4e, -163 dBm Channels Update rate (default) 1 Hz max (fix rate configurable) Supply voltage, VDD +1.71…... -
Page 10: Absolute Maximum Ratings
2010-06-30 Page 10 of 42 IT430_Tech_doc.doc 2.2 Absolute Maximum Ratings Absolute Maximum Ratings Table 2 Item unit Operating and storage temperature ºC Power dissipation Supply voltage, VDD -0.3 +2.2 Supply voltage, VDD_ANT -5.5 +5.5 Supply current, VDD_ANT (must be +150 externally limited) Input voltage on any input connection -0.3... -
Page 11: Operation
IT430_Tech_doc.doc OPERATION 3.1 Operating modes After power up the IT430 module boots from the internal ROM to Hibernate state. The module operation requires ON_OFF interrupt to wakeup for Normal (Navigation, Full on) mode. Modes of operation: • Full on (Navigation, Full Power) Power management system modes •... -
Page 12: Hibernate State
2010-06-30 Page 12 of 42 IT430_Tech_doc.doc every 1800 sec) to receive new ephemeris data from rising satellites or if received signal levels drop below certain level. 2. Advanced Power Management (APM): APM allows power savings while ensuring that the quality of the solution is maintained when signal levels drop. APM does not engage until all necessary information is received. -
Page 13: Reset State
2010-06-30 Page 13 of 42 IT430_Tech_doc.doc Hibernate state. The host must send the CGEE data back to the module after wake up from Hibernate state. 3.4 Reset state Reset state is entered internally after power up until the internal RTC clock wakes up after which internal reset state is relaxed. -
Page 14: Connectivity
2010-06-30 Page 14 of 42 IT430_Tech_doc.doc CONNECTIVITY 4.1 Signal assignments The I/O signals are available as soldering (castellated) pads on the bottom side of the module. These pads are also used to attach the module on the motherboard. All I/O signal levels are 1.8V CMOS compatible and inputs are 3.6V tolerable. - Page 15 2010-06-30 Page 15 of 42 IT430_Tech_doc.doc used. RTS_N S,C,B, S,C,B, PU - GPIO7 PU(a) - SPI_SS_N slave SPI chip select (CS#), active low - UART_RTS_N UART ready to send (RTS), active low - Host port boot strap, see 4.3 Can be left unconnected when not used.
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Page 16: Power Supply
I/O type depending on the firmware function. 4.2 Power supply The IT430 module requires only one power supply VDD. Keep the supply active all the time in order to keep the non-volatile RTC & RAM active for fastest possible TTFF. - Page 17 Switcher mode via sending a binary message from the host (Message ID 178 TrackerIC, Sub ID 2 TrackerConfig; contact Fastrax support for details). By-pass the VDD supply input by a low ESR ceramic de-coupling capacitor (e.g. 4.7 uF) placed nearby VDD pin to ensure low ripple voltage at VDD.
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Page 18: Host Port Configuration: Rts_N And Cts_N
2010-06-30 Page 18 of 42 IT430_Tech_doc.doc VDD supply ripple voltage: 54 mV(RMS) max @ f = 0… 3MHz and 15 mV(RMS) max @ f > 3 MHz. 4.3 Host Port Configuration: RTS_N and CTS_N User can select the host port configuration between UART, SPI (slave) and I C (master/slave) during power up boot. -
Page 19: Host Port I C
2010-06-30 Page 19 of 42 IT430_Tech_doc.doc ■ The receiver FIFO is not empty ■ The receiver FIFO fill level does not exceed the alarm level ■ There are no received FIFO input for a programmable number of SPI source clock ticks 4.3.3 Host Port I The I²C host port interface supports: ■... -
Page 20: Reset Input
2010-06-30 Page 20 of 42 IT430_Tech_doc.doc Figure 2 Suggested ON_OFF Hibernate control timing diagram. NOTE Do not generate multiple ON_OFF interrupts less than 1 sec intervals. Especially filter out multiple pulses generated by a mechanical switch bounce. 4.5 Reset input The RESET_N (active low) signal provides external override of the internally generated power up/down reset. -
Page 21: Active Gps Antenna
Other features will follow like Pedestrian DR. When sensor is used connect also the sensor’s INT output to IT430’s EIT2 input. The bus signals require external pull up resistors 2.2kohm on both signals and can be left not connected when not used. -
Page 22: Time Mark Tm
The firmware may support optionally other output functions from TM signal, like GPS_ON output for e.g. external LNA power control or RTC_CLK, which outputs buffered RTC clock signal at 32768 Hz; contact Fastrax support for details. WAKEUP The WAKEUP output signal provides indication to e.g. external power supply when full power is required by the module. -
Page 23: Eit2
2010-06-30 Page 23 of 42 IT430_Tech_doc.doc 4.10.2 EIT2 The EIT2 signal is available as either an edge triggered or a level triggered interrupt, while EIT is only available as a level triggered interrupt. Either high or low levels or either rising edge or falling edge are programmable as the active condition on EIT2. - Page 24 2010-06-30 Page 24 of 42 IT430_Tech_doc.doc Figure 3 Dimensions...
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Page 25: Test Points
2010-06-30 Page 25 of 42 IT430_Tech_doc.doc Figure 4 I/O pad numbering and dimensions, bottom view. 4.14 Test points On the bottom side of the module there are also test points TP1… TP8, which are reserved for production testing. Leave these test points floating (not connected) and unsoldered. -
Page 26: Suggested Pad Layout
2010-06-30 Page 26 of 42 IT430_Tech_doc.doc 4.15 Suggested pad layout Figure 5 Suggested pad layout and occupied area, top view. Suggested paste mask openings equal pad layout. -
Page 27: Manufacturing
MANUFACTURING 5.1 Assembly and soldering The IT430 module is intended for SMT assembly and soldering in a Pb-free reflow process on the top side of the PCB. Suggested solder paste stencil height is 150um minimum to ensure sufficient solder volume. If required paste mask pad openings can be increased to ensure proper soldering and solder wetting over pads. -
Page 28: Module Variants
5.3.1 Module variants The IT430 module is available in two variants based on firmware feature set. Note that by default IT430 is shipped with Signature feature set and Basic feature set variant is available only on request. -
Page 29: Tape And Reel
2010-06-30 Page 29 of 42 IT430_Tech_doc.doc 5.4 Tape and reel One reel contains 500 modules. Figure 6 Tape and reel specification... -
Page 30: Reference Design
The following picture describes a minimum connectivity for a typical autonomous navigation application. It consists of the IT430 module, which is powered by the main VDD supply (+1.8 V). The external by-pass capacitor C1 is used to de-couple the VDD supply pin. -
Page 31: Pcb Layout Issues
The suggested 4-layer PCB build up is presented in the following table. Suggested PCB build up Table 5 Layer Description Signal + RF trace + Ground plane with solid copper under IT430 Ground plane for signals and for RF trace Signals and power planes Ground plane (also short traces allowed) - Page 32 The serial resistors at the I/O should be placed very near to the IT430 module. In this way the risk for the local oscillator leakage is minimized. For the same reason by-pass capacitors C1 and C2 should be connected very close to the module with short traces to IO contacts and to the ground plane.
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Page 33: It430 Application Board
The Fastrax IT430 Application Board provides the IT430 connectivity to the Fastrax Evaluation Kit or to other evaluation purposes. It provides a single PCB board equipped with the IT430 module, a 1.8V regulator, a 4 channel level translator for 1.8V I/O to 3.3V conversion, an MCX antenna connector, and a 2x20 pin Card Terminal connector. - Page 34 Not connected Ground Not connected Ground TSYNC Timesync timing input, VDD 1.8V Ground ECLK ECLK clock input, VDD 1.8V Ground Inverted ON_OFF control input, ON_OFF_N ON_OFF (inv.) pulled up to VDD_3V3 Alternative GPIO Interface to Fastrax Evaluation Signal name name...
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Page 35: Bill Of Materials
2010-06-30 Page 35 of 42 IT430_Tech_doc.doc 7.2 Bill of materials Item Reference Part Name C/0402/NPO/27P/50V/T5P,27pF C/0402/X5R/100N/6V3/T20,100nF C/0402/X5R/100N/6V3/T20,100nF C/0402/X5R/1U/6V3/T20,1uF C/0402/X7R/10N/50V/T10P,10nF C/0402/X7R/10N/50V/T10P,10nF C/0402/X7R/10N/50V/T10P,10nF C/0805/X5R/4U7/6V3/T5P,4u7F C/0805/X5R/4U7/6V3/T5P,4u7F C/0805/X5R/4U7/6V3/T5P,4u7F C/0805/X5R/4U7/6V3/T5P,4u7F C/0805/X5R/4U7/6V3/T5P,4u7F FIDUCIAL,FIDUCIAL FIDUCIAL,FIDUCIAL HOL/M3.0 Hole M/3.0mm , metallized HOL/M3.0 Hole M/3.0mm , metallized IT430_APP_TP,IT430A01 J/1X2/0/2P54,1x2P2.54 J/1X2/0/2P54,1x2P2.54 J/2X20/EDGE,2x20 edge J/2X5/2P54,2x5P2.54... - Page 36 2010-06-30 Page 36 of 42 IT430_Tech_doc.doc R/0402/10K/T5P/G,10k, 5% R/0402/10K/T5P/G,10k, 5% R/0402/10K/T5P/G,10k, 5% R/0402/10K/T5P/G,10k, 5% R/0402/10K/T5P/G,N/A R/0402/10K/T5P/G,N/A R/0402/10K/T5P/G,N/A R/0402/10K/T5P/G,N/A R/0402/15K/T1P/G,15k, 1% R/0402/2K2/T5P/G, 2.2kohm, 5% R/0402/2K2/T5P/G, 2.2kohm, 5% R/0402/1K5/T5P/G,N/A R/0402/1K5/T5P/G,N/A R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/220R/5P/G,220R, 5% R/0402/33K/1P/G,33k 1% R/0402/47R/T5P,47R, 5%...
- Page 37 2010-06-30 Page 37 of 42 IT430_Tech_doc.doc R/0402/47R/T5P,47R, 5% R/0402/47R/T5P,47R, 5% R/0402/47R/T5P,47R, 5% R/0402/47R/T5P,47R, 5% R/0402/47R/T5P,47R, 5% S/JMP/1X2,J4/P1-P2 SW/2M54,SW JMP 2P54 SW/2M54,SW JMP 2P54 SW/2M54,SW JMP 2P54 SW/2M54,SW JMP 2P54 SW/2M54,SW JMP 2P54 SW/PUSHBUTTON,SW U/EEPROM/M24M01,M24M01-RMN6TP U/FXL4TD245,FXL4TD245 U/LOGIC/NC7S14,NC7SZ14M5X U/REG/ADJ/TPS79101,TPS79101...
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Page 38: Circuit Drawing
2010-06-30 Page 38 of 42 IT430_Tech_doc.doc 7.3 Circuit drawing... -
Page 39: Assembly Drawing, Top Side
2010-06-30 Page 39 of 42 IT430_Tech_doc.doc 7.4 Assembly drawing, Top side 7.5 Artwork, layer 1 (Top) -
Page 40: Artwork, Layer 2
2010-06-30 Page 40 of 42 IT430_Tech_doc.doc 7.6 Artwork, layer 2 7.7 Artwork, layer 3... -
Page 41: Artwork, Layer 4 (Bottom)
2010-06-30 Page 41 of 42 IT430_Tech_doc.doc 7.8 Artwork, layer 4 (Bottom) - Page 42 2010-06-30 Page 42 of 42 IT430_Tech_doc.doc Contact Information Fastrax Ltd. Street Address: Valimotie 7, 01510 Vantaa, FINLAND Tel: +358 (0)424 733 1 Fax: +358 (0)9 8240 9691 http://www.fastraxgps.com E-mail: Sales: sales@fastraxgps.com Support: support@fastraxgps.com...
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