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hilscher netX 50 Migration Manual

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Migration Guide
netX 50 to netX 51/52
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public

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Summary of Contents for hilscher netX 50

  • Page 1 Migration Guide netX 50 to netX 51/52 Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 2: Table Of Contents

    Comparison netX 50 with netX 51/52 ....................12 Overview ............................12 2.1.1 Block Diagrams ..........................12 2.1.2 Key Features ........................... 13 2.1.3 Enhancements of netX 51/52 against netX 50 ................14 Package, Pinning, Pad Cells .......................15 netX 52 ............................15 3.1.1 netX 52 Package ..........................15 3.1.2 netX 52 Pinning ..........................

  • Page 3: Introduction

    1 Introduction Migration from netX 50 to netX 51/52 This manual describes the differences between the netX 50 and netX 51/52 with the aim to support and lead you during the migration from netX 50 to netX 51/52. Real-Time-Ethernet / Fieldbus...
  • Page 4 0,50 € Material Cost per Interface in quantities of 10.000 pcs. without PCB 16,00 € Table 1: Material Costs netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 5: List Of Revisions

    This corresponds to the convention of the Microsoft C Compiler. All IP addresses in this document have host byte order. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 6: Netx Signal Description

    Reset Boundary Scan Controller TEST Activate Test Mode (left open) TMC1 Test Mode 1 (left open) TMC2 Test Mode 2 (left open) netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 7 Memory Data 0-31 MEM_A0...23 Memory Address 0-23 Host Interface DPM_A00...15 Dual-Port Memory Address 0..15 DPM_BE1n Dual-Port Memory Byte High Enable netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 8 Reference Resistor 12.4 k / 1% PHY_ATP Leave open! PHY_VSSACP PHY Analog Central Ground Supply PHY_VDDCAP PHY Analog Central Power Supply 1.5 V netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 9 ETM_TPKT13 ETM Trace packet 13 ETM_TPKT14 ETM Trace packet 14 ETM_TPKT15 ETM Trace packet 15 Table 4: Signal Description netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 10: Legal Notes

    There is no entitlement to revisions of delivered documents. The manual delivered with the product applies. Hilscher Gesellschaft für Systemautomation mbH is not liable under any circumstances for direct, indirect, incidental or follow-on damage or loss of earnings resulting from the use of the information contained in this publication.

  • Page 11: Exclusion Of Liability

    1.4.3 Exclusion of Liability The software was produced and tested with utmost care by Hilscher Gesellschaft für Systemautomation mbH and is made available as is. No warranty can be assumed for the performance and flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user.

  • Page 12: Comparison Netx 50 With Netx 51/52

    Block Diagram netX 50 Figure 3: Block Diagram of netX 50 Block Diagram netX 51/52 Figure 4: Block Diagram of netX 51/52 netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 13: Key Features

    2.1.2 Key Features The netX 51 and netX 52 is an enhancement of the existing netX 50 to fulfil the increasing demands of performance and functionality of industrial networks. These controllers are supporting the PROFINET Specification 2.3 with the new option of Dynamic Frame Packaging and the IO-Link Version 1.1 with long telegrams.

  • Page 14: Enhancements Of Netx 51/52 Against Netx 50

     Support of XiP (Execution in Place). Execution of program code directly out of serial flash netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 15: Package, Pinning, Pad Cells

    3 Package, Pinning, Pad Cells The netX 51 comes in a 324 pin PBGA package and has the same pinning and size as the netX 50 has. It is designed to replace the netX 50 without changing the PCB (drop-in-replacement).

  • Page 16: Netx 52 Pinning

    Dual-Port Memory Data 20 IOU9 DPM_D21 Dual-Port Memory Data 21 IOU9 DPM_D22 Dual-Port Memory Data 22 IOU9 DPM_D23 Dual-Port Memory Data 23 netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 17 Reserved n. c. Reserved n. c. Reserved n. c. Reserved n. c. Reserved n. c. Reserved n. c. Reserved netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 18 PHY 1 Transmit Output positive PHY Transceiver PHY1_TXP PHY 1 Transmit Output negative APWR PHY1_VDDCART PHY 1 Power Supply Core 1.5V netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 19 Power Supply IO 3.3V 3,3V IO Power VDDIO POWER Power Supply IO 3.3V 3,3V IO Power VDDIO POWER Power Supply IO 3.3V netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 20 POWER Power Supply Ground Ground POWER Power Supply Ground Ground POWER Power Supply Ground Ground POWER Power Supply Ground netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 21 USB_VDDC USB Power Supply Core 1.5 V USB_VDDIO USB Power Supply IO 3.3 V Table 7: netX 52 Pinning netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 22: Alternative Function At Host Interface

    IOD9 SD_CLK SDRAM Clock IOU9 SD_CKE SDRAM Clock Enable IOU9 MII_RXD0 MII Data Interrupt IOU9 MII_RXD1 MII Data 13 netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 23 MII Data 11 IOU9 MII_MDC MII Data 12 IOU9 PIO52 Peripheral IO Table 8: Alternative Function at Host Interface netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 24: Netx 51

    This new functions are disabled after power up or reset that the netX 51 has the same behaviour as the netX 50. To use these features these have to be enabled by software.
  • Page 25 An internal multiplex can be activated to change these address lines into the SIO2 and SIO3 signals for the Quad SPI mode and the MEM_A18 and MEM_A19 functionality moves to the highest address lines. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 26 QSPI_SIO3 Table 12: Differences in Pinning and Pad Cells – SPI If a Quad SPI flash is used for fast start up at netX 50 the already published workaround via the communication controller is working also with netX 51. In addition the netx 51 includes a very fast Quad SPI controller which also support “execution in place”...
  • Page 27 Table 13: Differences in Pinning and Pad Cells – USB In USB device mode the netX 50 requires an external resistor to connect USB hosts. This resistor is activated either using a MMIO in software or via jumper during bootstrap situation.
  • Page 28 IOU9 SPM_DIRQn MMIO44 DPM_D13 IOU9 SPM_SIRQn MMIO45 DPM_D14 IOU9 SPM_SIO2 MMIO46 DPM_D15 IOU9 SPM_SIO3 MMIO47 DPM_D16 IOU9 DPM_D17 IOU9 netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 29 The Ethernet signals emulate a PHY with a MII Interface in the way that every CPU with an integrated MAC can be used for data transfer. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...
  • Page 30 IODS6 ETM_TPKT10 FO0_SD MMIO35 IODS6 ETM_TPKT11 FO0_TD MMIO36 IODS6 ETM_TPKT12 FO1_EN MMIO37 IODS6 ETM_TPKT13 FO1_RD MMIO38 IODS6 ETM_TPKT14 FO1_SD netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 31 Digital Ground (0 V) APWR Analog power (1.5V or 3.3V) AGND Analog ground (0 V) Table 16: Pad Type Explanation netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 32: Mmio Signals

    MII1 MII1_TXCLK Input MII1 MII1_TXD0...3 Tristate able output MII1 MII1_TXEN Tristate able output MII1 MII1_TXER Tristate able output MII1 netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 33 A second I2C controller is implemented special for accessing the fiber optic transceiver in PROFINET communication  The additional USB signals are no more necessary because netX 50 has only s USB device and the USB pin becomes a function to pull the USB line high. ...

  • Page 34: General Changing

    The xPIC is also used for the IO-Link controller and the additional third Ethernet MAC channel. In this cases the xPIC not available user applications. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 35: Memory

    For example to access INTRAM1 via I-TCM interface the start address is 0x00020000 and via D-TCM interface is 0x04020000. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 36: Peripherals

     PHY-Mode: direct connection to Host via MII w/o ext. PHY  Datalink Layer realized via xPIC  Multiplexed to MMIO and HIF pins netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 37 Additionally supported serial DPM via SPI/QSPI  SPI modes 0...3, up to 125 MBaud Integrated SDRAM Controller Table 20: Peripheral Comparison netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 38: Improved Memory Access Performance

    So the user application has to run non-cached out of external memory which leads to a weak access performance (see benchmark table below). The netX 51/52 has following changes regarding to netX 50:  Internal SRAM enlarged from 96 KByte to 672 KByte ...

  • Page 39: Activating 256 Kbyte As Dual-Port Memory And Detection Of Netx 51 Or Netx 52 Mode

    For netX 51 and netX 52 the firmware must be updated in any case! The netX 51 provides all signals from the die. The pinning is identical to the netX 50 and the chip can be placed instead of a netX 50 on the PCB.

  • Page 40: Host Interface Modes

    40/56 Host Interface Modes The selection of the Host Interface Mode is a new feature of netX 51/52 compared to netX 50. These options are a simple way to configure the host interface if the Security Memory is not used.

  • Page 41: Miscellaneous

    Linkable Objects  Operating Systems compilations 4.7.3 Effects to existing Development Tools Due the netX 51/52 has another netX version and is not software-compatible to the netX 50 (different memory and register outlet) please note:  New Hitop-PlugIn required ...

  • Page 42: Erratas

    GPIO module: Interrupts may be lost Internal PHYs: Error in 10 Mbit half duplex mode Host Interface: DPM access time with Hilscher standard DPM layout is unpredictable Table 24: Fixed Erratas of netX 50 netX 50 to netX 51/52 | Migration Guide...

  • Page 43: New Errata For Netx 51 / 52

    In new designs this can be compensated by connecting the Cathode of the SYS LED instead the Anode according the schematic below. This LED interface is exactly the same as for the netX 10. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 44: Simultaneous Operation Of Sdram And Parallel Flash Memory At The Memory Interface

    SDRAM memory and parallel Flash Memory at the Host Interface at the same. time. Maximum load capacity for SDRAM at the Host Interface is 30 pF. netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public...

  • Page 45: Design Examples

    Design Examples 45/56 6 Design Examples Design Example netX 51 Figure 6: Design Example netX 51 – COM Interfaces netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 46 Design Examples 46/56 Figure 7: Design Example netX 51 – Core/Memory netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 47 Design Examples 47/56 Figure 8: Design Example netX 51 – Ethernet - Diagport netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 48 Design Examples 48/56 Figure 9: Design Example netX 51 – 2-Port Ethernet netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 49 Design Examples 49/56 Figure 10: Design Example netX 51 – Power Supply netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 50: Design Example Netx 52

    Design Examples 50/56 Design Example netX 52 Figure 11: Design Example netX 52 – Top View netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 51 Design Examples 51/56 Figure 12: Design Example netX 52 – Host Interface netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 52 Design Examples 52/56 Figure 13: Design Example netX 52 – CPU Core netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 53 Design Examples 53/56 Figure 14: Design Example netX 52 – Ethernet Interface netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...
  • Page 54 Design Examples 54/56 Figure 15: Design Example netX 52 – Power Supply netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

  • Page 55: Appendix

    Figure 1: Functionality and Price of netX 6/50/51/52......................3 Figure 2: Design Example with netX 51 ..........................4 Figure 3: Block Diagram of netX 50 ..........................12 Figure 4: Block Diagram of netX 51/52 ..........................12 Figure 5: Mechanical Dimensions of the netX 52 ......................15 Figure 6: Design Example netX 51 –...

  • Page 56: Contacts

    Phone: +1 630-505-5301 E-Mail: info@hilscher.it E-Mail: info@hilscher.us Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: it.support@hilscher.com E-Mail: us.support@hilscher.com netX 50 to netX 51/52 | Migration Guide DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public 2012-2013...

This manual is also suitable for:

Netx 51Netx 52

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