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—
2-6 Sync. ID
When
no signal
is received
the
voltage
on
pin 14 of IC101
changes
to "Low".
As a
consequence,
D783 and Q718 are turned on, and a "High" is supplied to pin 20 of the CPU.
As a result, the CPU judges that no signal is being received.
In the AV mode, the CPU
outputs a "High" signal from pin 51 to drive the blue back function.
CPU
SYNC. ID 20
E!zE5E9
SHARPNESS 7
Q718
a
R785
5.6k
Iclol
Chroma/Def.
14 SHARPNESS
:4
.. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. .
—;
Sharpness control
~ D/A circuit
. ......................................
L
2-7 Bus control
This chassis
uses the IPC bus as the interface for operation
control between
ICS, and the
CPU is used as the master for operation control of the Teletext decoder, A2 Stereo decoder,
Nicam decoder and Memory IC.
The IPC bus is composed
of the SCL(Serial
Clock Line) and SDA(Serial
Data Line) lines.
Data is transmitted
over the SDA line in 8-bit units in synchronisation
with the SCL line.
These lines are also used for the option function. When the TV set turns on, the CPU once
sends the slave address of the Teletext IC, Nicam IC and Stereo IC via the SDA line and
waits the ACK(Acknowledge)
signal from each IC.
The CPU judges which decoder is available by receiving the ACK signal.
CPU
SCL 12
SDA 13
R746
3.9k
d
IC790
Memory IC
6 SCL
5 SDA
AAl -A
.
AA1-A
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