Genesys GL3520 Design Manual
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Genesys GL3520 Design Manual

Usb 3.0 hub controller
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Genesys Logic, Inc.
USB 3.0 Hub Controller
Design Guide
Revision 2.11
Jan. 06, 2015

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Summary of Contents for Genesys GL3520

  • Page 1 Genesys Logic, Inc. USB 3.0 Hub Controller Design Guide Revision 2.11 Jan. 06, 2015...
  • Page 2 USB 3.0 Hub Design Guide Copyright Copyright © 2015 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc.

  • Page 3: Genesys Logic, Inc. - All Rights Reserved

    Updated CH2 Circuit Design and PCB Layout Guidelines 2.00 10/02/2013 Updated CH3 System Design Guidelines 2.10 01/05/2015 Updated Figure 3.4, p.25 01/06/2015 Correct page number in 2.10 Revision History 2.11 © 2015 Genesys Logic, Inc. - All rights reserved. Page 3 GLI Confidential...

  • Page 4: Table Of Contents

    2.8.2 USB 2.0 ......................18 2.8.3 Recommend Width and Space for USB 2.0 & USB3.0 Trace ....18 2.9 GL3520/GL3521 Co-Layout Notice ............... 19 2.10 GL3521 Layout Notice ..................... 20 © 2015 Genesys Logic, Inc. - All rights reserved. Page 4 GLI Confidential...
  • Page 5 3.3 Channel Description – without a Cable ..............24 3.4 Hub Trace on Mother Board .................. 25 4. ESD PROTECTION ......................26 4.1 Hub ..........................26 4.2 Hub with External Charger IC ................26 © 2015 Genesys Logic, Inc. - All rights reserved. Page 5 GLI Confidential...

  • Page 6: Introduction

    0603 (0402 is recommended). And AC coupling capacitor must be placed symmetrically. (as shown in Fig. 2.1) Perferred example Bad example Figure 2.1 © 2015 Genesys Logic, Inc. - All rights reserved. Page 6 GLI Confidential...

  • Page 7: Pcb Layer And Material

    2.3.3 Differential Trace Length Preliminary Guidelines Differential Pairs Signal Referencing Trace Mismatch Tolerance Maximum Total Length USB 3.0 ≦5mil Ground 9 inches SSTXP/N, SSRXP/N USB 2.0 ≦50mil Ground 9 inches DP/DM © 2015 Genesys Logic, Inc. - All rights reserved. Page 7 GLI Confidential...

  • Page 8: Trace Bend

    (See Fig. 2.3) SS Traces on Top Layer USB Connector USB HUB Controller Top Layer Full Ground Layer (Better) Power or Ground Layer Bottom Layer Figure 2.3 © 2015 Genesys Logic, Inc. - All rights reserved. Page 8 GLI Confidential...

  • Page 9: Signal Return Path

    An incorrect signal return path is one of the most common sources for noise coupling and EMI problems. Source Sink Signal: Source to Sink Signal Return Path: Sink to Source Figure 2.5 Return Current tries to follow the Signal Path © 2015 Genesys Logic, Inc. - All rights reserved. Page 9 GLI Confidential...
  • Page 10 If the forward and return paths of a signal are separated, the area between them acts as a loop antenna. Figure 2.6 Avoid Routing over Split Planes © 2015 Genesys Logic, Inc. - All rights reserved. Page 10 GLI Confidential...

  • Page 11: Differential Pair Layout

    Perferred example Via placement is symmertic and in same location Bad example Via placement is not symmertic / in same location Figure 2.8 © 2015 Genesys Logic, Inc. - All rights reserved. Page 11 GLI Confidential...

  • Page 12: Avoid Stub On Differential Traces

    If TXN and TXP swap function is needed for layout concern, Hub firmware needs to be modified accordingly. The “TXP/N Swap” function MUST be selected in Configuration of the Genesys Logic USB 3.0 Hub FW ISP Tool at the same time. Choose the port whose TXN and TXP traces is swapped. (as shown in Fig 2.11)
  • Page 13 USB 3.0 Hub Design Guide Figure 2.11 © 2015 Genesys Logic, Inc. - All rights reserved. Page 13 GLI Confidential...

  • Page 14: Circuit And Component Placement

    * Capacitors should be located near the IC 2.4.2 RTERM Resistor RTERM reference resistor use 680 ohm ±1% and place as close to the IC as possible. © 2015 Genesys Logic, Inc. - All rights reserved. Page 14 GLI Confidential...

  • Page 15: Crystal Circuit

    The crystal traces shall be symmetrical and parallel in order to get better oscillation wave form and better EMI protection (as shown in Fig. 2.13). Figure 2.13 2.4.4 Reset Circuit Keep the Reset circuit placement as close to the IC as possible. © 2015 Genesys Logic, Inc. - All rights reserved. Page 15 GLI Confidential...

  • Page 16: Power Source

    6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND. Figure 2.14 © 2015 Genesys Logic, Inc. - All rights reserved. Page 16 GLI Confidential...

  • Page 17: Power Trace Of Charging Downstream Port

    (0.5mm) to reduce chip thermal impact. Top View Bottom View Chip ground VIA Diameter ─ 0.5mm VIA to VIA gap ─ 50 mil © 2015 Genesys Logic, Inc. - All rights reserved. Page 17 GLI Confidential...

  • Page 18: Trace Width And Adjacent Space Gap

    *Note: The trace width (W) / spacing (S) may be different by PCB material characteristic base on PCB Vendor suggest. Differential Pair Setting 1 Setting 2 Trace width (W) 6mil 8mil Intra pair spacing (S) 6mil 7mil Target impedance 90 Ohm ± 10 % © 2015 Genesys Logic, Inc. - All rights reserved. Page 18 GLI Confidential...

  • Page 19: Gl3520/Gl3521 Co-Layout Notice

    GPIO (PAMBER#). The width of DVDD12 power trace line is recommended to be 40 mils, and the width of DVDD33 power trace line is to be 30 mils. Figure 2.18 Figure 2.19 © 2015 Genesys Logic, Inc. - All rights reserved. Page 19 GLI Confidential...

  • Page 20: Gl3521 Layout Notice

    Please reduce at least 2 vias when the 5V or 12V power trace is needed to go through different layers. Please refer to the Fig. 2.22 for more detailed information. Figure 2.20 Figure 2.21 © 2015 Genesys Logic, Inc. - All rights reserved. Page 20 GLI Confidential...
  • Page 21 5V power source Top Layer: Minimum 2 via hole L1 Inductance Bottom Layer: 1.2V power source to USB3.0 HUB Top layer Color Bottom layer Color Figure 2.22 © 2015 Genesys Logic, Inc. - All rights reserved. Page 21 GLI Confidential...

  • Page 22: System Design Guidelines

    Panel Connector Front 8" Internal Cable Panel Connector A. Host Reference Design Connector Connector 6" PCB Trace Test Point B. Device Reference Design Figure 3.1 Compliance Channel © 2015 Genesys Logic, Inc. - All rights reserved. Page 22 GLI Confidential...

  • Page 23: Channel Description - With A Cable

    -20dB (It is equal to 9-inch (-2.664dB) + 3m (-13.2dB) + 6-inch (-1.776dB) + -2dB (-1dB/mated connectors)), and also need to take care about crosstalk (NEXT, FEXT). Finally, the HUB PCB design must pass compliance channel testing. © 2015 Genesys Logic, Inc. - All rights reserved. Page 23 GLI Confidential...

  • Page 24: Channel Description - Without A Cable

    So, keeping 9 -inch and 6-inch FR4 trace length can gain much margin. © 2015 Genesys Logic, Inc. - All rights reserved. Page 24...

  • Page 25: Hub Trace On Mother Board

    Fig. 3.4 The recommended length of Hub trace is up to 9 -inch on the mother board. However, if the Host trace length is less than 9- inch, use the shorter one of these two numbers. © 2015 Genesys Logic, Inc. - All rights reserved. Page 25...

  • Page 26: Esd Protection

    Figure 4.1 4.2 Hub with External Charger IC 4.2 shows the suggested layout guide if the external charger IC is implemented for battery charging function. Figure 4.2 © 2015 Genesys Logic, Inc. - All rights reserved. Page 26 GLI Confidential...

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