Dg-Board (4 Of 4) Block Diagram - Panasonic TH-58PZ750U Service Manual

TH-58PZ750U

15.26. DG-Board (4 of 4) Block Diagram

DG DIGITAL SIGNAL PROCESSOR
MICOM
HDMI INTERFACE
FULL HD
21
22
23
24
MVCLK-CLKIA
MVSYNC-VSIA
MHSYNC-HSIA
ROE2-GYIA3
ROE3-GYIA1
ROE4-GYIA4
ROE5-GYIA0
ROE6-GYIA7
ROE7-GYIA6
ROE8-GYIA2
ROE9-GYIA5
HQ1_XRST
IC5851
FHD3.3V
LVDS RECEIVER
VCC
RxOUT20 54
TO
DG8
JG08
RxOUT18 51
RA- 6 9 RxIN0- RxOUT15 47
RA+ 7 10 RxIN0+
RxOUT12 43
RB- 9 11 RxIN1- RxOUT9 39
RB+ 10 12 RxIN1+ RxOUT8 38
RC- 12 15 RxIN2-
RxOUT6 35
RC+ 13 16 RxIN2+ RxOUT4 34
15 17 RxCLKIN-
RCLK- RxOUT0 27
16 18 RxCLKIIN+
RCLK+
RxCLKOUT 26
RxOUT22 1
RxOUT21 55
FOR
FACTORY DG4
USE
WP 2
SCL 4
SDA 5
TH-58PZ750U
DG-Board (4 of 4) Block Diagram
IC5001
IC5002
AVR 3.3V
SUB5V
DDR 2.5V
1 VDD VOUT 5
CE
FHD3.3V
5 VOUT
3
IC5012
AVR 3.3V VDDA_PLL_DDR AVDD_DDRCLK AVDD_DDR
1 VDD VOUT 5 DAC_VDD
CE VDD_PLL2
3
FHQCKIN
VDD_PLL1
FHQVIN
VDDW
FHD1.2V
FHQHIN
PORT-THQ
VDD12
FHQYIN0-9
CLKIA
FHQCIN0-9
CLKIA
VSIA
VSIA
PORT-A
CLK0THQ1
HSIA
HSIA
(ADV)
THQVOUT
THQHOUT
RVIA0-7
GYIA0-7
THQYO0-9
GOE2-RVIA3 BOE2-RVIA1
BUIA0-7
GOE3-BUIA3 BOE2-BUIA1
THQCO0-9
GOE4-BUIA7 BOE2-BUIA0
GOE5-BUIA4 BOE2-RVIA2
X5000
XTALOUT
GOE6-BUIA6 BOE2-BUIA2
GOE7-RVIA7 BOE2-RVIA0
XTALIN
GOE8-RVIA5 BOE2-RVIA4 IC5100
GOE9-RVIA6 BOE2-BUIA5
GC5P_1st FRCK02
NRST
H264_UV2-UV9
PORT-E
OSDI0-7
PTVEN
H264_Y2-Y9
CLK0E
(OUTPUT
OSDI8-15
VS0E
FOR PANEL)
H264_CLK
HS0E
PORT-D
CLKID
H264_V
(H264)
VSI BOE0-9
H264_H
HSI GOE0-9
ROE0-9
TRST
VDD25
TCK
H264_UV2-UV9 JTAG
TMS
TDI(TO_HQ1L) DQ0-DQ31
TDO
ADDRESS BUS
A0-A11
SCL0 SCL
SDA0 SDA
BA0,BA1
H264_Y2-Y9 DQS0-DQS3 CONTROL BUS
SCL_MC
CKE,WE
RAS,CAS
SDA_MC
SDCLK0,NSDCL0
H264_CLK
H264_V
H264_H
IC5000
64k EEPROM
FHD3.3V
7 WC VCC 8
6 SCL
5 SDA
TV_MAIN_ON
16 27 17
CTL CB1 CB2
30
OVP
18 OUT2-1
FHD9V
20 OUT2-2
G2 S2 G1 S1
19 LX2
D2 D2 D1 D1
TV_MAIN_ON
8 -INC2
Q5902
FHD1.2V
12 VO2
11 FB2
FHD3.3V
VDD 1
Q5001
SCL0
Q5000
SDA0
FPGA_XRST
LVDS_PD
CONFIG_DONE
PEAKS_OSDCK
PEAKS_OSDH
PEAKS_YS
PEAKS_YM
PEAKS_OSVO
PEAKS_OSHO
PEAKS_OSCKO
OSD_FLAG
PEAKS_OSD0-OSD15
FRCK_FPGA
IC5013
RESET
FHD3.3V
2 VDD OUT 4
DATA BUS
DQ0-DQ31 IC5003
OSD-FIFO
FHD3.3V
A0-A11
BA0,BA1 VCC
VDD
DQS0-DQS3 DATA BUS
VDDQ
DI0-DI31
CKE,WE
RAS,CAS
DATA BUS
CK,CK
DO0-DO31
SRCK,SWCK CONTROL BUS
IC5102 RSTR,RSTW
RE,WE
DDR-SDRAM
IC5006
AVR 2.5V
FHD3.3V
1 VOUT VDD 8
100
IC5901
DC-DC CONVERTER
SUB(FHD)9V
9V->1.2V,9V->3.3V
21
VB
23
VCC
OUT1-1 26
OUT1-2 24
G2 S2 G1 S1
LX1 25
D2 D2 D1 D1
-INC1 7
Q5901
VO1 3
FHD3.3V
FB1 4
IC5009 IC5008
AVR 2.5V AVR 1.5V
FHD3.3V
8 VIN VOUT 1 8 VIN VOUT 1
VDDI01 VDDI02 VDDI04
SCL
SDA VDDI03
VCCINT
NRST VCCA_PLL1
VCCA_PLL2
LVDS_PD
CONF_DONE
PEAKS_OSDCK
PEAKS_OSDH
PEAKS_YS
PEAKS_YM
IC5105
PEAKS_OSVO
FPGA
PEAKS_OSHO
(CYCLONE) RE_E+
PEAKS_OSCKO
RE_E-
OSD_FLAG RD_E+
RD_E-
RC_E+
PEAKS
RC_E-
OSD0-15
RB_E+
RB_E-
RA_E+
FRCLKIN
27MHz RA_E-
RCLK E+
RCLK E-
NCFG
RCLK O+
PTVEN
RCLK O-
CLK0E
VS0E RE O+
HS0E
RE O-
RD O+
BOE0-9
RD O-
GOE0-9
RC O+
ROE0-9
RC O-
RB O+
RB O-
RA O+
RA O-
IC5010
FHD3.3V CONFIG ROM
3 VCC
DCLK 6 DCLK
ASDO 5 ASDI
OSD_DI0-DI31
DATAO 2 DATA
OSD_DO0-31
nCSO 1 NCS
OSD_SRCK,SWCK
OSD_RSTR,RSTW
OSD_RE,WE TCK
CFG-JTAG
TMS
TDI
TDO
TH-58PZ750U
DG-Board (4 of 4) Block Diagram
DG5 TO D5
1 E+LVDS0
2 E-LVDS0
4 E+LVDS1
5 E-LVDS1
6 E+LVDS2
7 E-LVDS2
9 E+LVDS3
10 E-LVDS3
11 E+LVDS4
12 E-LVDS4
14 E+LVDSCLK
15 E-LVDSCLK
16 LVDS_DET
17 0+LVDSCLK
18 0-LVDSCLK
20 0+LVDS0
21 0-LVDS0
23 0+LVDS1
24 0-LVDS1
25 0+LVDS2
26 0-LVDS2
28 0+LVDS3
29 0-LVDS3
30 0+LVDS4
31 0-LVDS4