Pleora Technologies iPORT PT1000-ST Hardware Manual

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Page 1 PT1000-ST Hardware Guide...
Page 3 ...proven performance...
Page 4 These products are not intended for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Pleora Technologies Inc. (Pleora) customers using or selling these products for use in such applica- tions do so at their own risk and agree to indemnify Pleora for any damages resulting from such improper use or sale.
Page 5: Table Of Contents
Contents Product summary: iPORT..................... 3 Overview: Connector names..................7 Overview: Signal names ....................9 Connector summary: OEM: PT1000-ST ..............17 Connector: LAN: Copper .................... 19 Connector: Power: Hirose HR10 6-pin ..............23 Connector: Power: Molex 4 ..................25 Connector: Raw video: 2x 40-pin connector ............27 Schematics: OEM: PT1000-ST ...................
Page 7: Product Summary: Iport
PC with the low, predictable end-to-end latency you require for your high-quality imaging and video systems. Pleora’s innovative packet re-send technology ensures all image data arrives safely to your PC. Data is never lost. Copyright © 2008 Pleora Technologies Inc.
Page 8 ANL is an abbreviation of analog. Camera Link video. The Camera Link standard is widely used for machine vision applications, such as bottle inspection or mail sorting. CL is an acronym for Camera Link. Copyright © 2008 Pleora Technologies Inc.
Page 9 A bare board similar to the ST, but with a form factor designed to fit into the back of a small camera. The VB is designed to receive raw video directly from a camera’s PCB. VB is an acronym for vertical board (the LAN connector rises vertically from the PCB). Copyright © 2008 Pleora Technologies Inc.
Page 11: Overview: Connector Names
Firmware selection 1. OEM versions of the PT1000-ANL use a header connector. Thus, you can receive many standard analog video inputs while maintaining a smaller footprint than would be possible with many BNC connectors. Copyright © 2008 Pleora Technologies Inc.
Page 12 The Firmware connector lets you choose if the IP Engine boots with its standard firmware or its backup (typically emergency) firmware. Serial connector Serial connectors provide a dedicated serial communication between the IP Engine and another component. Internal use connector Internal use connectors have no customer-usable pins. Copyright © 2008 Pleora Technologies Inc.
Page 13: Overview: Signal Names
PWR........................... 12 RET..........................12 Reserved........................11 RXD ........................... 16 SCK..........................16 SCL ..........................16 SER_HBx_CLK......................15 SER_HBx_RX ......................15 SER_HBx_TX ......................15 SER_SBx_RX......................15 SER_SBx_RX- ......................15 SER_SBx_RX+ ......................15 SER_SBx_RX_RS232....................16 SER_SBx_TX ......................15 Copyright © 2008 Pleora Technologies Inc.
Page 14: Signal Type And Direction
Signal level/standard tors) ANALOG_VIDchannel_input CVBS/S-Video DGND Power DVCC Power DVCC_SEL Power/In GND_ANALOG_VID GND_CHASSIS Power GND_FLTRD Power LVDS_IN- LVDS LVDS_IN+ LVDS OPTx_IN- Opto OPTx_IN+ Opto OPTx_OUT- Opto OPTx_OUT+ Opto Power Power LVCMOS/LVTTL LVCMOS/LVTTL LVCMOS/LVTTL SER_HBx_CLK LVCMOS/LVTTL Copyright © 2008 Pleora Technologies Inc.
Page 15: Internal Signals
Driving signals high, low, or using them as inputs may cause erratic behavior and may permanently damage the IP Engine. Never connect to a reserved signal unless specif- ically instructed to do so. Copyright © 2008 Pleora Technologies Inc.
Page 16: Power
The SYSTEM_PWR_ON_RST# can also be used as an input to the IP Engine. By holding the signal low, you can keep the IP Engine in its reset state (idle) until the camera is ready. You can use this case if the IP Engine boots faster than the camera. Copyright © 2008 Pleora Technologies Inc.
Page 17: Video Control: Generic
Not all cameras output all signals; for analog cameras, the signals are generated by the video decoder chip. As a general rule, the IP Engine’s image grabber can acquire images properly as long as it receives the LVAL signal. Copyright © 2008 Pleora Technologies Inc.
Page 18: Video: Analog
DC source. LVDS is tolerant of electrically noisy environments and can transmit reliably at high rates. LVDS doesn’t always refer to these two signals – for example, both Camera Link and LVDS cameras transmit video data over many LVDS pairs. Copyright © 2008 Pleora Technologies Inc.
Page 19: Serial Communication
C mode SER_HBx_RX Receive data Receive data SER_HBx_TX Transmit data Transmit data Data SER_HBx_CLK Serial clock Serial clock SER_SBx_RX- SER_SBx_RX+ SER_SBx_TX- SER_SBx_TX+ The SER_SBx_RX and SER_SBx_TX signals, using differential signal pairs instead of DGND. Copyright © 2008 Pleora Technologies Inc.
Page 20: Rxd
The SERx_RX and SERx_TX signals as RS232 level signals. Levels conform to the Electronic Industries Alliance Recommended Standard 232 (EIA RS-232-C). Signal levels are with respect to DGND. Mode-specific names for High-Bandwidth Serial signals. See SER_HBx_RX. Copyright © 2008 Pleora Technologies Inc.
Page 21: Connector Summary: Oem: Pt1000-St
See “Connector: LAN: Copper” on page 19. Power See “Connector: Power: Molex 4” on page 25. Raw video J1, J3 See “Connector: Raw video: 2x 40-pin connector” on page 27. Internal Leave unconnected Copyright © 2008 Pleora Technologies Inc.
Page 23: Connector: Lan: Copper
VB-series, Ethernet jack (RJ45) Xmultiple XRJV-S-01-8-8-5 www.xmultiple.com NTx-Mini horizontal Ethernet jack (RJ45) Halo Electronics Inc. HFJ11-1G01E-L11RL www.haloelectronics.com XFMRS Inc. XFGIB100JM-CLGG1-4MS www.xfmrs.com NTx-Mini vertical Ethernet jack (RJ45) ERNI 203346 www.erni.com NTx-Pro, Ethernet jack (RJ45) Halo HFJ11-1G11E-L11RL www.haloelectronics.com Copyright © 2008 Pleora Technologies Inc.
Page 24 The LAN_CU* signal names are based on standard pinouts and standard behavior. The signal names aren’t used elsewhere in this manual. TIA/EIA-568-B T568B cable wiring Conventional Pair - wire Color signal name White/orange LAN_CU_TX+ Orange LAN_CU_TX- Copyright © 2008 Pleora Technologies Inc.
Page 25 Green LAN_CU_RX- White/brown LAN_CU_TRD3+ Brown LAN_CU_TRD3+ Shell GND_CHASSIS (enclosed IP Engines only) a. The LAN_CU* signal names are based on standard pinouts and standard behavior. The signal names aren’t used elsewhere in this manual. Copyright © 2008 Pleora Technologies Inc.
Page 27: Connector: Power: Hirose Hr10 6-Pin
Connector components Part description Part number 6-pin connector (with pins) Hirose Electric HR10A-7R-6P(73) Mating components Part description Part number 6-pin connector (with sockets) Hirose Electric HR10A-7P-6S(73) Pinouts Connector pinouts Signal name 1,2,3 4,5,6 Shell GND_CHASSIS Copyright © 2008 Pleora Technologies Inc.
Page 29: Connector: Power: Molex 4
Part description Part number 4-pin shell (with sockets) Molex 22-01-3047 Crimp sockets (quantity 4) Molex 08-55-0102 Pinouts Connector pinouts Signal name Pinouts when looking at IP Engine (top view) Maximum current per pin: 4000 mA Copyright © 2008 Pleora Technologies Inc.
Page 31: Connector: Raw Video: 2X 40-Pin Connector
2x20 pin interboard IO receptacle (x2) Hirose Electric FX6-40S-0.8SV2(71) Mating components Part description Part number 2x20-pin interboard IO header (x2) Hirose Electric FX6-40P-0.8SV2(71) Pinouts Connector pinouts for J3 Signal name DGND DGND VIDEO_CLK0 VIDEO_DATA0 VIDEO_DATA1 VIDEO_DATA2 Copyright © 2008 Pleora Technologies Inc.
Page 32 SER_HB0_TX SER_HB0_CLK VIDEO_DATA15 VIDEO_DATA11 VIDEO_DATA12 VIDEO_DATA13 DVCC DVCC VIDEO_DATA16 VIDEO_DATA22 VIDEO_DATA23 VIDEO_DATA17 DGND DGND VIDEO_DATA18 SYSTEM_FW_SEL SYSTEM_CLK SYSTEM_PWR_ON_RST# DGND DGND Connector pinouts for J1 Signal name DGND DGND Reserved VIDEO_DATA19 VIDEO_DATA20 VIDEO_DATA21 DGND DGND Copyright © 2008 Pleora Technologies Inc.
Page 33 Q4 (aka VIDEO_CC1) Reserved Reserved Reserved Q5 (aka VIDEO_CC2) Q6 (aka VIDEO_CC3) Q7 (aka VIDEO_CC4) Q3_NOT (Inverse of Q3) DVCC DVCC A3_NOT (Inverse of A3) DGND DGND Reserved DGND DGND Maximum current per pin: 500 mA Copyright © 2008 Pleora Technologies Inc.
Page 37: Firmware: Generation 1
Firmware Selection connector; others provide it on the Raw Video connector. (If your IP Engine is an enclosed unit, you must remove the enclosure and consult the hardware guide for the OEM version of your IP Engine.) Turn on the IP Engine. Copyright © 2008 Pleora Technologies Inc.
Page 38 Flash memory Main firmware Backup firmware With the firmware loaded, the IP Engine is ready to: • Acquire images • Use the LAN connection • Use the PLC Booting takes under 1 second. Copyright © 2008 Pleora Technologies Inc.
Page 39 (many firmware updates reset automatically). When the IP Engine reboots, the EPLD loads the new firmware into the FPGA and the changes take effect. IP Engine SYSTEM_FW_SEL Config bus EPLD FPGA Main Flash bus firmware Flash memory Main firmware Backup firmware Copyright © 2008 Pleora Technologies Inc.
Page 40 IP Engines or traffic). (For an iPORT IP Engine, see the iPORT Quick Start Guide.) Disconnect your PC from your office network and disable any wireless connectivity. Run the Firmware Updater and follow the instructions it provides. Copyright © 2008 Pleora Technologies Inc.
Page 41: Timing: Pixel Bus
NTx-Mini values are 4.5 ns typ. To obtain the exact width, use clock period at 40% duty cycle. b. NTx-Mini values are 90 MHz and 11 ns. To obtain exact clock period, use 1/frequency. Copyright © 2008 Pleora Technologies Inc.
Page 42 Case 3: VIDEO_FVAL is edge-sensitive and VIDEO_LVAL is level-sensitive FV2FV FI2FV FV2DV FV2FI VIDEO_FVAL LV2LI VIDEO_LVAL FV2LV LLI2DV LI2LV VIDEO_DVAL (N-1, (N-1, VIDEO_DATAx (0,0) (1,0) (N,0) (0,1) (1,1) (N,M) (0,0) (1,0) LI2DV Don’t Care Window Size = N x M LV2DV DI2LI Copyright © 2008 Pleora Technologies Inc.
Page 43 This is a worst-case value. Subtract 3 cycles if the pixel type is 8-bit, 1-tap. Subtract 1 cycle for all other pixel types except 10/12-bit, 2-tap, unpacked, and RGB unpacked. Subtract up to 7 cycles if the image size is a multiple of 32 bytes. Copyright © 2008 Pleora Technologies Inc.
Page 45: Timing: Plc
• TTL* • All PLC signals that remain within the PLC (see the iPORT Programmable Logic Controller Reference Guide). PLC signal PLC Signals Maximum Parameter Symbol Minimum (ns) (ns) PLC Signal pulse width none Copyright © 2008 Pleora Technologies Inc.
Page 47: Timing: Serial Port: High-Bandwidth Serial: Uart, Usrt, And I2C
Serial communication” on page 79. High-Bandwidth Serial: USRT The USRT (universal synchronous receiver/transmitter) serial interface resembles the UART interface, but adds a clock signal to enable synchronous communication. USRT signal nomenclature IP Engine signal Generic signal SER_HBx_RX Copyright © 2008 Pleora Technologies Inc.
Page 49 A - not acknowledge (SDA high) R - read (SDA high) S - START Condition - from master to slave P - STOP Condition - from slave to master Sr - STOP/START or Repeated START Condition n - BufferSize Copyright © 2008 Pleora Technologies Inc.
Page 51: Timing: Serial Port: Standard-Bandwidth: Uart
UART (bps) (us) 8170 122.4 9600 113.2 14400 69.4 19200 52.1 28800 34.7 38400 26.0 57600 17.4 115200 a. Baud rate is based on the inverse of the data period, or t =1/BR UART Copyright © 2008 Pleora Technologies Inc.
Page 53: Status Leds: Overview
In the iPORT Vision Suite, set the CY_GRABBER_PARAM_TAP_QUANTITY parame- ter; in the iPORT PureGEV Suite, set the SensorDigiti- zationTaps feature. a. The component consists of two independently operated LEDs. Under normal viewing, the LEDs appear as a single LED. Copyright © 2008 Pleora Technologies Inc.
Page 54 LED; the green LED is typically not discernible when the orange LED is active. Network connection speed LED Network connection speed LED Significance No connection, 10 Mbps connection, or 100 Mbps con- nection. Green 1 Gbps connection. Copyright © 2008 Pleora Technologies Inc.
Page 55 For Tx: ASI data stream being sent by the IP Engine. (The LED blinks regardless of a cable being connected.) Firmware status LED Firmware status LED (Style 4) Significance The IP Engine’s firmware is corrupted. Orange blinking Using main firmware. Orange Using backup firmware. Copyright © 2008 Pleora Technologies Inc.
Page 57: Status Leds: Location: Pt-Series
For the behavior of the LEDs, see “Status LEDs: Overview” on page 49. Network Network Power connection activity speed ST-based LEDs and component IDs Component ID Network connection speed LED Network Activity LED (Style 1) Power LED (Style 1) Copyright © 2008 Pleora Technologies Inc.
Page 59: Specifications: Gen. 1 & 2
IP Engine doesn’t boot. In all cases, ensure the enclosure maintains very low humidity (dry air) to avoid condensation damage. b. Presumes free air flow. In enclosed environments, ensure that local temperatures don’t exceed this rating. Copyright © 2008 Pleora Technologies Inc.
Page 60 80 MHz SER_SBx_RX_ Input voltage, absolute max -25 V 25 V RS232 range All other pins Input voltage, absolute max -0.5 V DVCC + 0.5 V range SER_SBx_RX_ Input voltage, signal low 0.8 V RS232 Copyright © 2008 Pleora Technologies Inc.
Page 61 Misc. mechanical specifications Description Specification Enclosure material Anodized aluminum Mounting holes Located as per drawing; diameter 0.17 (Fits #8 or M4 machine screws) PCB thickness 0.0625 Maximum height of components 0.08, except where noted Copyright © 2008 Pleora Technologies Inc.
Page 63: Specifications: Programmable Logic Controller
Input voltage, absolute max range minimum: -0.5 V maximum: 7.0 V Input voltage maximum low 0.99 V Input voltage minimum high 2.31 V ESD HBM (human-body model) 2000 V ESD protection (V 5.1 V zener Copyright © 2008 Pleora Technologies Inc.
Page 64: Ttl_Outx
LVDS_IN+ Rload LVDS_IN- LVDS_INx specifications Specification Value Maximum input frequency 16.5 MHz Termination resistor (R 100 ohms load Input current minimum: -10 uA maximum: 10 uA Input voltage minimum: 0.0 V maximum: 3.0 V Copyright © 2008 Pleora Technologies Inc.
Page 65: Optx_In
Below is the test circuit used to measure response times. Vtest IO Block IO Block TI SN74LS244N Optically Isolated Input Block OPT_IN+ OPT_IN- OPT_IN response-time test circuit specifications Specification Value Edge response time Rising: 2.11 us Falling: 30.56 us Copyright © 2008 Pleora Technologies Inc.
Page 66: Optx_Out
Minimum: 0.5 V Maximum: 5.0 V Edge response time Rising: 32.89 us Falling: 2.89 us a. To improve rising-edge response time (at the expense of a higher minimum output voltage), reduce R ’s resistance. pullup Copyright © 2008 Pleora Technologies Inc.
Page 67: System Design: Onboard Memory
Buffer section of the iPORT C++ SDK Reference Guide, or use the following simplified equation. The value of packingFactor is either 1.0 or 0.75. ⋅ ⋅ ⋅ imageFootprintInBytes pixelsX pixelsY effectivePixelDepth packingFactor Round imageFootprintInBytes up to the nearest 32 bytes. Copyright © 2008 Pleora Technologies Inc.
Page 68 Calculate the number of images your IP Engine can store in its onboard memory. An IP Engine with 16MB of memory has 16 * 1024 bytes. ⋅ 31 IPEngineOnboardMemoryInBytes ----------------------------------------------------------------------------------------------------- - maximumNumberOfImagesInMemory ⋅ 32 imageFootprintInBytes Truncate maximumNumberOfImagesInMemory. Copyright © 2008 Pleora Technologies Inc.
Page 69: System Design: Supported Nics
To test if your new PRO/1000 NIC is (unofficially) supported in the iPORT Vision Suite: Open the INF file for your preferred driver. See “Testing if your PRO/1000 chipset is officially supported” on page 65. Save a copy of filename.inf as filename.inf.bak. Copyright © 2008 Pleora Technologies Inc.
Page 70 Intel PRO/1000 MT Server Adapter Copper PCI-X PWLA8490MT Intel PRO/1000 MF Dual Port Server Adapter Fiber PCI-X PWLA8492MF Intel PRO/1000 MF Server Adapter Fiber PCI-X PWLA8490MF Intel PRO/1000 MF Server Adapter (LX) Fiber PCI-X PWLA8490LX Copyright © 2008 Pleora Technologies Inc.
Page 71 Sample supported Intel PRO/1000 NICs NIC name and order code Ethernet type Ports Slot type Intel PRO/1000 XF Server Adapter Fiber PCI-X PWLA8490XF Intel PRO/1000 XT Server Adapter Copper PCI-X PWLA8490XT PWLA9490XTL (low profile) Copyright © 2008 Pleora Technologies Inc.
Page 73: System Design: Ethernet Switches
Before specifying any switch for your system, test it thoroughly. Switches and features Jumbo Switch model and manufacturer IGMP v2.0 Layer frames Tigerswitch 86xxT family www.smc.com 3C1740x (3800 family) 3COM www.3com.com Copyright © 2008 Pleora Technologies Inc.
Page 74 70 System design: Ethernet switches Switches and features Jumbo Switch model and manufacturer IGMP v2.0 Layer frames DGS-10xxTx 10/100/1000 family D-Link www.dlink.com 3C1770x (4900 family) 3COM www.3com.com DGS-3308FG and DGS-3308-TG D-Link www.dlink.com WS-C3750G-12S-S Cisco www.cisco.com DGS-3324SR D-Link www.dlink.com Copyright © 2008 Pleora Technologies Inc.
Page 75: System Design: Pc Requirements
PC). The IP Engine’s PLC lets you create a system that works with realtime, deterministic accuracy, even with a non-realtime operating system. To use the PLC, see the iPORT Programmable Logic Controller Reference Guide. Copyright © 2008 Pleora Technologies Inc.
Page 77: Oem Design: Camera Link Pixel Bus Definitions
Reserved The following are the bit assignments for YUV color. YUV color bit assignments YUV 4:2:2 YUV 4:2:2 YUV 4:2:2 Signal name YUV 4:4:4 (8 bit) (10 bit) (12 bit) VIDEO_DATA0 VIDEO_DATA1 VIDEO_DATA2 VIDEO_DATA3 Copyright © 2008 Pleora Technologies Inc.
Page 78 UV10 VIDEO_DATA15 Reserved UV11 VIDEO_DATA16 Reserved VIDEO_DATA17 Reserved VIDEO_DATA18 Reserved VIDEO_DATA19 Reserved VIDEO_DATA20 Reserved VIDEO_DATA21 Reserved VIDEO_DATA22 Reserved VIDEO_DATA23 Reserved a. To use this mode, use 2 taps and assign the signals as shown. Copyright © 2008 Pleora Technologies Inc.
Page 79: Oem Design: Controlling Emi
Filter the PWR/RET lines with a ferrite cable core. We recommend 2 turns around (3 times through the core) a 154 Ohm @ 100 MHz ferrite core. We recommend that you use the ferrite cable core included on our enclosed IP Engines: part number 28B0375-100 from Steward, a Copyright © 2008 Pleora Technologies Inc.
Page 80 • the enclosure’s cover, baseplate, and backplate. • the enclosure’s baseplate and the LAN connector. • the enclosure’s backplate and the video connector (if required for your IP Engine). Copyright © 2008 Pleora Technologies Inc.
Page 81: Oem Design: Firmware Selection
To learn more about firmware loads, see “Understanding the main and backup firmware loads” on page 33. The IP Engine’s circuitry includes an internal pull-up resistor ensures the main firmware by default. IP Engine DVCC Raw video connector SYSTEM_FW_SEL DGND Copyright © 2008 Pleora Technologies Inc.
Page 82 If you want to always use the main firmware, use the following design. IP Engine DVCC Camera Raw video connector SYSTEM_FW_SEL DGND Make no connection Note that should the firmware become corrupted, recovery would be non-trivial (because the SYSTEM_FW_SEL signal can’t easily be shorted to DGND). Copyright © 2008 Pleora Technologies Inc.
Page 83: Oem Design: Serial Communication
...then acknowledges the successful transmission to the PC (via Ethernet). Camera IP Engine Standard-Bandwidth Serial Standard-Bandwidth Serial transfers each character in a message one-character-at-a-time. Due to latencies associated with sending and receiving messages via Ethernet (while very fast), the effective Copyright © 2008 Pleora Technologies Inc.
Page 84 IP Engine and another device. • You can download UART, USRT, or I C serial-control cores from www.opencores.org. Serial protocols at a glance UART Universal asynchronous receiver/transmitter. Copyright © 2008 Pleora Technologies Inc.
Page 85 (such as a second IP Engine, second camera, or serially controlled Pan/tilt/zoom equipment), use I Design: I C requires an external pull-up resistor on the SDA (SER_HBx_TX) and SCL (SER_HBx_RX) line loads (typically 10 kohm). Copyright © 2008 Pleora Technologies Inc.
Page 87: Oem Design: Power Supply
Connect DGND to your camera for all designs. To minimize EMI, connect all available DGND pins to your camera • Don’t filter DGND between the IP Engine and the camera – such designs are likely to cause reference-level problems. Copyright © 2008 Pleora Technologies Inc.
Page 88: Design 1: Separate Ip Engine And Camera Power
The IP Engine partially filters the voltage, but most of the regulation is dependent on the power supply attached to PWR. For best results, filter and regulate the VIN_FLRTD/GND_FLTRD signals before delivering them to the camera’s internal circuitry. Copyright © 2008 Pleora Technologies Inc.
Page 89: Design 3: Ip Engine Supplies Dvcc To The Camera
This arrangement bypasses the IP Engine’s preliminary filter, including a Zener diode used to minimize ESD damage and voltage spikes. Thus, filtering on the camera should also protect the voltage supplied to the IP Engine. Copyright © 2008 Pleora Technologies Inc.
Page 90: Design 5: Camera Supplies Dvcc To The Ip Engine
Ensure the camera can supply enough current to satisfy the IP Engine. • Short either PWR with RET or VIN_FLTRD with GND_FLTRD together. Otherwise, induced voltage could damage the filter between RET and GND_FLTRD. Copyright © 2008 Pleora Technologies Inc.
Page 91: Oem Design: Unused Pins: St-Series Ip Engines
The IP Engine’s PLC-related inputs include built-in weak pull-ups or pull-downs that control the voltage on unused input pins. Thus the PLC connector pins can be left unconnected. Shorting an output pin to ground or power can damage the IP Engine. Copyright © 2008 Pleora Technologies Inc.
Page 93: Oem Design: Prober Board
The prober board connects to an ST-series IP Engine (see “Connector: Raw video: 80-pin header” on page 105). The prober board features different connectors with identical pinouts - choose the connector that best suits your needs. In this section: Components ....................... 90 Pinouts ........................90 Copyright © 2008 Pleora Technologies Inc.
Page 94 Samtec (www.samtec.com) TCSD-08-xxxxxxx Pinouts Connector pinouts for both J22 and J24 Signal name VIDEO_DATA0 VIDEO_CC2 VIDEO_DATA1 DGND VIDEO_DATA2 DGND VIDEO_DATA3 DGND VIDEO_DATA4 DGND VIDEO_DATA5 VIDEO_CC1 VIDEO_DATA6 SER_SB0_TX VIDEO_DATA7 SER_SB0_RX VIDEO_DATA8 VIDEO_DATA27 VIDEO_DATA9 VIDEO_DATA26 VIDEO_DATA10 Copyright © 2008 Pleora Technologies Inc.
Page 95 VIDEO_DATA15 VIDEO_DATA16 Connector pinouts for both J25 and J27 Signal name VIDEO_CC3 SYSTEM_CLK VIDEO_CC4 DGND Reserved DGND SER_HB0_RX SER_HB0_TX SER_HB0_CLK A3_NOT (inverse of A3) Q3_NOT (inverse of Q3) DGND Reserved DGND DGND DGND DVCC Copyright © 2008 Pleora Technologies Inc.
Page 96 Signal name DVCC Reserved DVCC Reserved DVCC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pinouts for J23 connector Signal name SYSTEM_FW_SEL DGND Pinouts for connector J26 Signal name Copyright © 2008 Pleora Technologies Inc.
Page 97: Oem Design: Interface Reference
“Connector: Power: Molex 4” on page 25). The design also includes suggestions for capacitive filtering, and firmware selection using SYSTEM_FW_SEL. Signal names use historical internal nomenclature. Connectors are on bottom side of PCB (X-ray view) Copyright © 2008 Pleora Technologies Inc.

Pleora Technologies iPORT PT1000-ST Hardware Manual

Table of Contents

9 Overview: Signal Names

Specifications: Programmable Logic Controller

83 Oem Design: Power Supply

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