Denon DN-C620 Service Manual page 35

Q004 : BH15LB1WB
Q101 : R5S72630P200FP
SH-2A
CPU core
Cache
controller
Internal LCD bus
(IL bus)
LCD I/F I/O
Pin function
controller I/O ports
(PFC)
Port
General I/O
User
Power-down
debu in
mode
interface
control
(H-UDI)
Port
JTAG I/O
PIN No. PIN NAME
1 VIN Power source input
2 GND Ground
3 STBY Output voltage ON/OFF control (High:ON, Low:OFF)
4 N. C. No Connect
5 VOUT Voltage output
Floatin -point
unit (FPU)
Instruction Operand On-chip RAM
cache memory cache memory (hi h-speed)
8 Kbytes 8 Kbytes 64 Kbytes
LCD Bus state USB2.0 host/
controller controller function module
(LCDC) (BSC) (USB)
Port Port
External bus I/O USB bus I/O
External bus width USB clock input
mode input
Multi-function
Clock pulse Interrupt
timer pulse
enerator controller
unit 2
(CPG) (INTC)
(MTU2)
Port Port Port
RES input
EXTAL input Timer pulse I/O
MRES input
XTAL output
CKIO I/O
MMI input
Clock mode input
IRQ input
PINT input
IRQOUT output
Samplin
On-chip RAM SD host
rate
(retention) interface
converter
16 Kbytes (SDHI)
(SRC)
Port
SD card I/F I/O
FUNCTION
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
User break
UBCTRG output
controller
(UBC)
Direct memory
CD-ROM
Peripheral access
decoder
bus controller controller
(ROM-DEC)
(DMAC)
Compare
Serial
Watchdo Realtime
match
communication
timer clock
timer interface with FIFO
(WDT) (RTC)
(SCIF)
(CMT)
Port Port Port
WDTOVF
RTC_X1 input Serial I/O
RTC_X2 output
output
AND/NAND
flash memory D/A converter A/D converter
controller (DAC) (ADC)
(FLCTL)
Port Port Port
Flash memory Analo output Analo input
ADTRG input
I/F I/O
51
CPU bus
(C bus)
(I clock)
Internal CPU bus
(IC bus)
Internal bus
(I bus)
Internal DMA bus
(B clock)
(ID bus)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Synchronous
2
I C bus
serial commnication
interface 3
unit
(IIC3)
(SSU)
Port Port
2
Serial I/O I C bus I/O
Controller Serial
IEBusTM
area sound
controller
network interface
(IEB)
(RCAN-TL1) (SSI)
Port Port Port
IEBus input CAN bus I/O Serial I/O
Audio clock input