Denon DCD-1500AE Service Manual page 27

Pin Name I/O
51 TESTI I
52 TESTI I
53 TESTO O
54 VDC -
55 DSADML O
56 DSADMR O
57 BCKASL I
58 VSDSD -
59 BCKAI I
60 BCKAO O
61 PHREFI I
62 PHREFO O
63 ZDFL O
64 DSAL O
65 ZDFR O
66 DSAR O
67 V SD -
DD
68 ZDFC O
69 DSAC O
70 ZDFLFE O
71 DSASW O
72 VSDSD -
73 ZDFLS O
74 DSALS O
75 ZDFRS O
76 DSARS O
77 V SD O
DD
78 IOUT0 O
79 IOUT1 O
80 VSC -
81 IOUT2 O
82 IOUT3 O
83 VDC -
84 IOUT4 O
85 IOUT5 O
86 VSIO -
87 IANCO O
88 IFULL I
89 IEMPTY I
90 VDIO -
91 IFRM O
92 IOUTE O
93 IBCK O
94 VSC -
95 TESTI I
96 TESTI I
Input for TEST. It fixed to "L" potential.
Input for TEST. It fixed to "L" potential.
Output for TEST. (open)
+2.5V Power for CORE.
DSD Data output terminal for Lch Down Mix.
DSD Data output terminal for Rch Down Mix.
I/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master)
Ground terminal for DSD data output.
Bit clock input terminal for DSD data output.
Input a Bit clock into this terminal at the time of BCKASL="L" potential.
Bit clock output terminal for DSD data output.
Bit clock output from this terminal at the time of BCKASL="H" potential.
Reference phase signal input terminal for DSD output phase modulation.
Reference phase signal output terminal for DSD output phase modulation.
Lch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for Lch speaker.
Rch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for Rch speaker.
+3.3V Power for DSD data output.
Cch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for Cch speaker.
LFEch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for SWch speaker.
Ground for DSD data output.
LSch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for LSch speaker.
RSch zero-data detection flag (at the time of µcom setup).
It will be set to "H" if non-sound data continues 300 msecs.
DSD data output terminal for RSch speaker.
+3.3V Power for DSD data output.
Data output terminal 0 for IEEE1394 link chip I/F.
Data output terminal 1 for IEEE1394 link chip I/F.
Ground for CORE.
Data output terminal 2 for IEEE1394 link chip I/F.
Data output terminal 3 for IEEE1394 link chip I/F.
+2.5V Power for CORE.
Data output terminal 4 for IEEE1394 link chip I/F.
Data output terminal 5 for IEEE1394 link chip I/F.
Ground for I/O.
Transmission information data output terminal for IEEE1394 link chip I/F.
Data transmission hold request signal input terminal for IEEE1394 link chip I/F.
High speed transmission request signal input terminal for IEEE1394 link chip I/F.
+3.3V Power for I/O.
Frame reference signal output terminal for IEEE1394 link chip I/F.
Enable signal output terminal for IEEE1394 link chip I/F.
Data transmission clock output terminal for IEEE1394 link chip I/F.
Ground for CORE.
TEST input terminal. It fixed to "H" potential.
TEST input terminal. It fixed to "L" potential.
Functions
27
DCD-1500AE