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SMSC FlexPWR LAN8720 Specification Sheet

Small footprint rmii 10/100 ethernet transceiver with ip auto-mdix support
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PRODUCT FEATURES

Highlights
Single-Chip Ethernet Physical Layer Transceiver
(PHY)
Comprehensive flexPWR
— Flexible Power Management Architecture
— Power savings of up to 40% compared to competition
— LVCMOS Variable I/O voltage range: +1.6V to +3.6V
— Integrated 1.2V regulator
HP Auto-MDIX support
Miniature 24 pin QFN lead-free RoHS compliant
package (4 x 4 x 0.85mm height).
Target Applications
Set-Top Boxes
Networked Printers and Servers
Test Instrumentation
LAN on Motherboard
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems/Routers
DSL Modems/Routers
Digital Video Recorders
IP and Video Phones
Wireless Access Points
Digital Televisions
Digital Media Adaptors/Servers
Gaming Consoles
POE Applications
SMSC LAN8720/LAN8720i
Small Footprint RMII 10/100
Ethernet Transceiver with HP
Auto-MDIX Support
®
Technology
DATASHEET
LAN8720/LAN8720i
Key Benefits
High-Performance 10/100 Ethernet Transceiver
— Compliant with IEEE802.3/802.3u (Fast Ethernet)
— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
— Loop-back modes
— Auto-negotiation
— Automatic polarity detection and correction
— Link status change wake-up detection
— Vendor specific register functions
Power and I/Os
— Various low power modes
— Integrated power-on reset circuit
— Two status LED outputs
— Latch-Up Performance Exceeds 150mA per EIA/JESD
78, Class II
— May be used with a single 3.3V supply
Advanced Features
— Able to use a low cost 25Mhz crystal for the lowest
eBOM
Packaging
— 24-pin QFN (4x4 mm) Lead-Free RoHS Compliant
package with RMII
Environmental
— Extended Commercial Temperature Range (0°C to
+85°C)
— Industrial Temperature Range (-40°C to +85°C) version
available (LAN8720i)
Datasheet
Revision 1.0 (05-28-09)

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Summary of Contents for SMSC FlexPWR LAN8720

  • Page 1: Product Features

    Digital Video Recorders IP and Video Phones Wireless Access Points Digital Televisions Digital Media Adaptors/Servers Gaming Consoles POE Applications SMSC LAN8720/LAN8720i LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Key Benefits High-Performance 10/100 Ethernet Transceiver — Compliant with IEEE802.3/802.3u (Fast Ethernet) —...
  • Page 2 Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

  • Page 3: Table Of Contents

    REF_CLK OUT Mode ........... 27 SMSC LAN8720/LAN8720i DATASHEET Revision 1.0 (05-28-09)
  • Page 4 Magnetics Selection ............75 Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support DATASHEET Datasheet SMSC LAN8720/LAN8720i...
  • Page 5 Chapter 10 Revision History ........... 79 SMSC LAN8720/LAN8720i Revision 1.0 (05-28-09)
  • Page 6 Figure 9.2 Reel Dimensions ............78 Revision 1.0 (05-28-09) SMSC LAN8720/LAN8720i DATASHEET...
  • Page 7 Table 6.1 SMI Timing Values............55 SMSC LAN8720/LAN8720i Revision 1.0 (05-28-09)
  • Page 8 Table 10.1 Customer Revision History ........... 79 Revision 1.0 (05-28-09) SMSC LAN8720/LAN8720i DATASHEET...

  • Page 9: Chapter 1 Introduction

    The LAN8720 referenced throughout this document applies to both the extended commercial temperature and industrial temperature components. The LAN8720i refers to only the industrial temperature component. SMSC LAN8720/LAN8720i 8-bits First In First Out buffer; often used for elasticity buffer Media Access Controller...

  • Page 10: Architectural Overview

    For example, the device can be set to 10BASE-T only. The LAN8720 supports both IEEE 802.3-2005 compliant and vendor-specific register functions. Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720 Ethernet Transceiver LED Status Crystal or Clock Osc DATASHEET Datasheet Transformer RJ45 Section 5.3.9. In addition, SMSC LAN8720/LAN8720i...

  • Page 11: Figure 1.2 Lan8720/Lan8720I Architectural Overview

    Control TXD[1:0] TXEN 100M Rx Logic RXD[1:0] Receive Section RXER 10M Rx Logic CRS_DV MDIO Figure 1.2 LAN8720/LAN8720i Architectural Overview SMSC LAN8720/LAN8720i 10M Tx Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- Clock Digital Data Recovery...

  • Page 12: Chapter 2 Pin Configuration

    XTAL1/CLKIN VDDCR Figure 2.1 LAN8720/LAN8720i 24-QFN Pin Assignments (TOP VIEW) Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support TXD1 SMSC TXD0 LAN8720/ TXEN LAN8720i 24 PIN QFN nRST (Top View) nINT/REFCLKO DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 13: Table 2.1 Lan8720/Lan8720I 24-Pin Qfn Pinout

    Datasheet Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout PIN NO. PIN NAME VDD2A LED2/nINTSEL LED1/REGOFF XTAL2 XTAL1/CLKIN VDDCR RXD1/MODE1 RXD0/MODE0 VDDIO RXER/PHYAD0 CRS_DV/MODE2 MDIO SMSC LAN8720/LAN8720i PIN NO. PIN NAME nINT/REFCLKO DATASHEET nRST TXEN TXD0 TXD1 VDD1A RBIAS Revision 1.0 (05-28-09)

  • Page 14: Chapter 3 Pin Description

    Note: The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V, as shown Table 7.1. Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 3.1. Table 3.1 Buffer Types DESCRIPTION DATASHEET Datasheet LAN8720/LAN8720i SMSC LAN8720/LAN8720i...

  • Page 15: Mac Interface Signals

    PIN # TYPE LED1/ IOPD REGOFF SMSC LAN8720/LAN8720i Table 3.2 RMII Signals 24-QFN DESCRIPTION Transmit Data 0: The MAC transmits data to the PHY using this signal in all modes. Transmit Data 1: The MAC transmits data to the PHY using this signal in...

  • Page 16: Management Signals

    This signal is mux’d with REFCLKO. Clock Input: Crystal connection or external clock input. Clock Output: Crystal connection. Float this pin when an external clock is driven to XTAL1/CLKIN. External Reset: Input of the system reset. This signal is active LOW. DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 17: 10/100 Line Interface Signals

    NAME PIN # TYPE VDDIO VDDCR VDD1A VDD2A FLAG SMSC LAN8720/LAN8720i DESCRIPTION Transmit/Receive Positive Channel 1. Transmit/Receive Negative Channel 1. Transmit/Receive Positive Channel 2. Transmit/Receive Negative Channel 2. Table 3.7 Analog References 24-QFN DESCRIPTION External 1% Bias Resistor. Requires an 12.1k resistor to ground connected as described in the Analog Layout Guidelines.

  • Page 18: Chapter 4 Architecture Details

    4 bits Encoder NRZI MLT-3 NRZI MLT-3 Converter Magnetics MLT-3 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Driver RJ45 CAT-5 MLT-3 SMSC LAN8720/LAN8720i...

  • Page 19: 5B Encoding

    Second nibble of SSD, translated to “0101” following J, else RXER 01101 First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RXER SMSC LAN8720/LAN8720i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001...

  • Page 20: Scrambling

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION DATASHEET Datasheet TRANSMITTER INTERPRETATION Sent for falling TXEN Sent for rising TXER INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN8720/LAN8720i...

  • Page 21: 100M Phase Lock Loop (Pll)

    The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN8720/LAN8720i 4B/5B 25MHz...

  • Page 22: Nrzi And Mlt-3 Decoding

    /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false. RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII mode). Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 23: Receiver Errors

    TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide 2.5MHz data. SMSC LAN8720/LAN8720i data data data data data data data data...

  • Page 24: Manchester Encoding

    The RX10M block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link. Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 50, for more details. DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 25: Receive Data Across The Mii/Rmii Interface

    4.6.1 RMII The SMSC LAN8720 supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet transceivers and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as the port counts increase.

  • Page 26: Reference Clock

    4.7.1. In the second mode, an advanced feature of the LAN8720 allows a low-cost 25MHz crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and is described in Section 4.7.2. Revision 1.0 (05-28-09) SMSC LAN8720/LAN8720i DATASHEET...

  • Page 27: Ref_Clk In Mode

    The LAN8720 is a small size, low pin count device. In order to optimize package size and cost, the REFCLKO pin is multiplexed with the nINT pin. Therefore, in this specific mode of operation, the nINT pin is disabled since REFCLKO is used to provide the 50MHz clock to the MAC. SMSC LAN8720/LAN8720i Figure LAN8720...

  • Page 28: Figure 4.5 Lan8720 Sources Ref_Clk From A 25Mhz Crystal

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720 MDIO 10/100 PHY 24-QFN TXD[1:0] RMII TXEN RXD[1:0] CRS_DV RXER REFCLKO XTAL1/CLKIN LED[2:1] XTAL2 nRST Figure 4.6. It is important to note that in this specific DATASHEET Datasheet RJ45 25MHz SMSC LAN8720/LAN8720i...

  • Page 29: Auto-Negotiation

    The advertised capabilities of the transceiver are stored in register 4 of the SMI registers. The default advertised by the transceiver is determined by user-defined on-chip signal options. The following blocks are activated during an Auto-negotiation session: Auto-negotiation (digital) SMSC LAN8720/LAN8720i LAN8720 10/100 PHY 24-QFN...
  • Page 30 Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8720/LAN8720i does not support “Next Page” capability. Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 31: Parallel Detection

    Auto-MDIX design. The Auto-MDIX function can be disabled using the Special Control/Status Indications register (bit 27.15). SMSC LAN8720/LAN8720i In this mode, If data is received while the transceiver is Figure 4.7, the SMSC LAN8720/LAN8720i Auto-MDIX DATASHEET Revision 1.0 (05-28-09)

  • Page 32: Nintsel Strapping And Led Polarity Selection

    Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 4.3 LED2/nINTSEL Configuration MODE REF_CLK DESCRIPTION nINT/REFCLK0 is the source of REF_CLK. nINT/REFCLK0 is an active low interrupt output. Figure 4.8. DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 33: Regoff And Led Polarity Selection

    REGOFF = 1 (Regulator OFF) LED output = active low VDD2A ~270 ohms LED1/REGOFF Figure 4.9 REGOFF Configuration on LED1 SMSC LAN8720/LAN8720i nINTSEL = 0 LED output = active high Figure 4.8 nINTSEL Strapping on LED2 REGOFF = 0 LED output = active high...

  • Page 34: Phy Address Strapping

    The timing relationships of the MDIO signals are further described in Interface (SMI) Timing," on page Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 4.10 Figure 4.11. DATASHEET Datasheet Section 6.1, "Serial Management SMSC LAN8720/LAN8720i...

  • Page 35: Figure 4.10 Mdio Timing And Frame Structure - Read Cycle

    32 1's Start of Preamble Frame Code Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle SMSC LAN8720/LAN8720i Read Cycle A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 PHY Address Register Address Data To Phy Write Cycle...

  • Page 36: Chapter 5 Smi Register Mapping

    Chapter 5 SMI Register Mapping Reset Loopback Speed Select Enable 100Base 100Base 100Base 10Base- Full Half Full Duplex Duplex Duplex PHY ID Number (Bits 3-18 of the Organizationally Unique Identifier - OUI) PHY ID Number (Bits 19-24 of the Organizationally Unique Identifier - OUI) Table 5.1 Control Register: Register 0 (Basic) Power...

  • Page 37: Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)

    Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended) Next Reserved Remote Reserved Page Fault Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended) Next Acknowledge Remote Reserved Page Fault Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended) Reserved Reserved Pause 100Base-...

  • Page 38: Table 5.10 Mode Control/ Status Register 17: Vendor-Specific

    Table 5.10 Mode Control/ Status Register 17: Vendor-Specific RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved Reserved MIIMODE Table 5.14 Symbol Error Counter Register 26: Vendor-Specific MDPREBP FARLOOPBACK RSVD ALTINT Table 5.11 Special Modes Register 18: Vendor-Specific Reserved Table 5.12 Register 24: Vendor-Specific Reserved Table 5.13 Register 25: Vendor-Specific Reserved...

  • Page 39: Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific

    Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL Reserved CH_SELECT Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific Reserved Reserved Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved GPO2 Reserved SQEOFF Reserved Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific INT7 INT6 Table 5.18 Interrupt Mask Register 30: Vendor-Specific...

  • Page 40: Smi Register Format

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 5.20 SMI Register Mapping DESCRIPTION DATASHEET Datasheet Group Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8720/LAN8720i...

  • Page 41: Table 5.21 Register 0 - Basic Control

    Auto-Negotiate 1 = auto-negotiate process completed 0 = auto-negotiate process not completed Complete SMSC LAN8720/LAN8720i Table 5.21 Register 0 - Basic Control DESCRIPTION when setting this bit do not set other bits in this register. The configuration (as described in Section 5.3.9.2) is set from the register bit values,...

  • Page 42: Table 5.23 Register 2 - Phy Identifier 1

    0 = no remote fault 00 = No PAUSE 01= Symmetric PAUSE 10= Asymmetric PAUSE toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local device DATASHEET Datasheet MODE DEFAULT MODE DEFAULT 0007h MODE DEFAULT DEVICE MODE DEFAULT SMSC LAN8720/LAN8720i...

  • Page 43: Table 5.26 Register 5 - Auto Negotiation Link Partner Ability

    Duplex 100Base-TX 10Base-T Full Duplex 10Base-T 5.4:0 Selector Field SMSC LAN8720/LAN8720i DESCRIPTION 1 = T4 able, 0 = no T4 ability This Phy does not support 100Base-T4. 1 = TX with full duplex, 0 = no TX full duplex ability...

  • Page 44: Table 5.27 Register 6 - Auto Negotiation Expansion

    100Base-TX only). This bit is only active in RMII mode, as described in Section 5.3.8.2. This mode works even if MII Isolate (0.10) is set. Write as 0, ignore on read. DATASHEET Datasheet MODE DEFAULT MODE DEFAULT 0001 MODE DEFAULT SMSC LAN8720/LAN8720i...

  • Page 45: Table 5.30 Register 18 - Special Modes

    PHYAD Table 5.31 Register 26 - Symbol Error Counter ADDRESS NAME 26.15:0 Sym_Err_Cnt SMSC LAN8720/LAN8720i DESCRIPTION Alternate Interrupt Mode. 0 = Primary interrupt system enabled (Default). 1 = Alternate interrupt system enabled. Section 5.2, "Interrupt Management," on page Write as 0, ignore on read.

  • Page 46: Table 5.33 Register 28 - Special Internal Testability Controls

    0 = not source of interrupt 1 = Auto-Negotiation LP Acknowledge 0 = not source of interrupt 1 = Parallel Detection Fault 0 = not source of interrupt DATASHEET Datasheet MODE DEFAULT NASR 000000 XXXXb MODE DEFAULT MODE DEFAULT SMSC LAN8720/LAN8720i...

  • Page 47: Table 5.35 Register 30 - Interrupt Mask

    Reserved 31.4:2 Speed Indication 31.1 Reserved 31.0 Scramble Disable SMSC LAN8720/LAN8720i DESCRIPTION 1 = Auto-Negotiation Page Received 0 = not source of interrupt Ignore on read. Table 5.35 Register 30 - Interrupt Mask DESCRIPTION Write as 0; ignore on read.

  • Page 48: Interrupt Management

    Interrupt Mask Register 30. The Interrupt system on the SMSC The LAN8720 has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT.

  • Page 49: Alternate Interrupt System

    The carrier sense is output on CRS. CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The LAN8720 asserts CRS based only on receive activity whenever the transceiver is either SMSC LAN8720/LAN8720i EVENT TO INTERRUPT SOURCE ASSERT nINT 17.1...

  • Page 50: Collision Detect

    When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic. 5.3.5 Power-Down modes There are 2 power-down modes for the LAN8720 described in the following sections. Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support DATASHEET Datasheet SMSC LAN8720/LAN8720i...

  • Page 51: Reset

    Software reset, and these are marked “NASR” in the register tables. The SMI registers are not reset by the power-down modes described in For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25 MHz if auto-negotiation is enabled.

  • Page 52: Figure 5.1 Near-End Loopback Block Diagram

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 5.1.The near-end loopback mode is enabled Analog SMSC XFMR Analog SMSC Figure 5.3. An RJ45 loopback cable can be used to route the DATASHEET Datasheet CAT-5 XFMR Link CAT-5 Partner SMSC LAN8720/LAN8720i...

  • Page 53: Configuration Signals

    5.21, the configuration of the 10/100 digital block is controlled by the register bit values, and the MODE[2:0] pins have no affect. The LAN8720 mode may be configured using hardware configuration as summarized in The user may configure the transceiver mode by writing the SMI registers. SMSC LAN8720/LAN8720i XFMR Analog SMSC DATASHEET RJ45 Loopback Cable.

  • Page 54: Table 5.39 Mode[2:0] Bus

    Table 5.40 Pin Names for Mode Bits MODE BIT PIN NAME MODE[0] RXD0/MODE0 MODE[1] RXD1/MODE1 MODE[2] CRS_DV/MODE2 DATASHEET Datasheet DEFAULT REGISTER BIT VALUES REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] 0000 0001 1000 1001 1100 0100 1100 0100 X10X 1111 Table 5.40. SMSC LAN8720/LAN8720i...

  • Page 55: Chapter 6 Ac Electrical Characteristics

    MDC to MDIO (Read from PHY) delay T1.3 MDIO (Write to PHY) to MDC setup T1.4 MDIO (Write to PHY) to MDC hold SMSC LAN8720/LAN8720i Valid Data (Read from PHY) Valid Data (Write to PHY) Figure 6.1 SMI Timing Diagram Table 6.1 SMI Timing Values...

  • Page 56: Rmii 10/100Base-Tx/Rx Timings (50Mhz Ref_Clk In)

    PARAMETER DESCRIPTION T6.1 Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Section 4.7.1. Valid Data DATASHEET Datasheet UNITS NOTES SMSC LAN8720/LAN8720i...

  • Page 57: Figure 6.3 100M Rmii Transmit Timing Diagram (50Mhz Ref_Clk In)

    Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T8.1 Transmit signals required setup to rising edge of CLKIN T8.2 Transmit signals required hold after rising edge of CLKIN CLKIN frequency SMSC LAN8720/LAN8720i Valid Data DATASHEET UNITS NOTES Revision 1.0 (05-28-09)

  • Page 58: Rmii 10Base-T Tx/Rx Timings (50Mhz Ref_Clk In)

    Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T9.1 Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Valid Data UNITS DATASHEET Datasheet NOTES SMSC LAN8720/LAN8720i...

  • Page 59: Figure 6.5 10M Rmii Transmit Timing Diagram (50Mhz Ref_Clk In)

    Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T10.1 Transmit signals required setup to rising edge of CLKIN T10.2 Transmit signals required hold after rising edge of CLKIN CLKIN frequency SMSC LAN8720/LAN8720i 10.1 10.2 Valid Data UNITS DATASHEET NOTES Revision 1.0 (05-28-09)

  • Page 60: Rmii 10/100Base-Tx/Rx Timings (50Mhz Ref_Clk Out)

    DESCRIPTION T11.1 Output delay from rising edge of REFCLKO to receive signals output valid REFCLKO frequency Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Section 4.7.2 11.1 Valid Data DATASHEET Datasheet UNITS NOTES SMSC LAN8720/LAN8720i...

  • Page 61: Figure 6.7 100M Rmii Transmit Timing Diagram (50Mhz Ref_Clk Out)

    Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION T12.1 Transmit signals required setup to rising edge of REFCLKO T12.2 Transmit signals required hold after rising edge of REFCLKO REFCLKO frequency SMSC LAN8720/LAN8720i 12.1 12.2 Valid Data DATASHEET UNITS NOTES Revision 1.0 (05-28-09)

  • Page 62: Rmii 10Base-T Tx/Rx Timings (50Mhz Ref_Clk Out)

    Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION T13.1 Output delay from rising edge of REFCLKO to receive signals output valid REFCLKO frequency Revision 1.0 (05-28-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 13.1 Valid Data UNITS DATASHEET Datasheet NOTES SMSC LAN8720/LAN8720i...

  • Page 63: Rmii Clkin Requirements

    REFCLKO CLKIN frequency RMII CLKIN Requirements Table 6.10 RMII CLKIN (REF_CLK) Timing Values PARAMETER DESCRIPTION CLKIN frequency CLKIN Frequency Drift CLKIN Duty Cycle CLKIN Jitter SMSC LAN8720/LAN8720i 14.1 14.2 Valid Data UNITS UNITS ± 50 DATASHEET NOTES NOTES psec p-p –...

  • Page 64: Reset Timing

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 11.1 11.2 11.3 11.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values DATASHEET Datasheet UNITS NOTES 20 clock cycles for 25 MHz clock 40 clock cycles for 50MHz clock SMSC LAN8720/LAN8720i...

  • Page 65: Clock Circuit

    The total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 MHz. SMSC LAN8720/LAN8720i SYMBOL AT, typ...

  • Page 66: Chapter 7 Dc Electrical Characteristics

    -0.5 +0.5 59.8 12.6 +150 ESD PERFORMANCE ±5 ±15 ±15 LATCH-UP PERFORMANCE DATASHEET Datasheet UNITS COMMENT Table 7.6 °C/W °C/W Extended commercial temperature components. Industrial temperature components. UNITS COMMENTS Device 3rd party system test 3rd party system test SMSC LAN8720/LAN8720i...

  • Page 67: Operating Conditions

    ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. SMSC contracts with Independent laboratories to test the LAN8720 to IEC61000-4-2 in a working system. Reports are available upon request. Please contact your SMSC representative, and request information on 3rd party ESD test results.

  • Page 68: Table 7.4 Power Consumption Device Only (Ref_Clk In Mode)

    Note 7.1 23.3 76.9 21.2 19.7 41.3 Note 7.1 24.4 20.4 15.2 Note 7.1 11.2 Note 7.1 Section 5.3.5 for a description Section 4.7.2 VDDIO TOTAL TOTAL POWER CURRENT POWER PIN(MA) (MA) (MW) 178.2 49.7 38.2 92.1 Note 7.3 SMSC LAN8720/LAN8720i...
  • Page 69 Note 7.3 This is calculated with full flexPWR features activated: VDDIO = 1.8V and internal regulator disabled. Note 7.4 Current measurements do not include power applied to the magnetics or the optional external LEDs. SMSC LAN8720/LAN8720i 12.8 11.3 DATASHEET 29.1 25.7 84.8...

  • Page 70: Dc Characteristics - Input And Output Buffers

    +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 VDDIO – +0.4 +8 mA +0.4 SMSC LAN8720/LAN8720i...

  • Page 71: Table 7.7 Lan Interface Signals

    The maximum input voltage on XTAL1/CLKIN is VDD2A + 0.4V. Table 7.11 Internal Pull-Up / Pull-Down Configurations NAME TXEN RXD0/MODE0 SMSC LAN8720/LAN8720i Table 7.7 LAN Interface Signals “10BASE-T Transceiver Characteristics,” on page Table 7.8 LED Signals 0.39 * VDD2A -12 mA 0.39 * VDD2A...

  • Page 72: Table 7.12 100Base-Tx Transceiver Characteristics

    PULL-UP OR PULL-DOWN Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-up Pull-up SYMBOL 1050 -950 -1050 SYMBOL DATASHEET Datasheet UNITS NOTES mVpk Note 7.6 mVpk Note 7.6 Note 7.6 Note 7.6 Note 7.6 Note 7.7 Note 7.8 UNITS NOTES Note 7.9 SMSC LAN8720/LAN8720i...

  • Page 73: Chapter 8 Application Notes

    The LAN8720 requires few external components. The voltage on the magnetics center tap can range from 2.5 - 3.3V. 8.1.1 RMII Diagram RMII MDIO nINT TXD[1:0] TXEN RXD[1:0] RXER LED[2:1] nRST Interface Figure 8.1 Simplified Application Diagram SMSC LAN8720/LAN8720i LAN8720 10/100 PHY 24-QFN RMII XTAL1/CLKIN XTAL2 DATASHEET RJ45 25MHz Revision 1.0 (05-28-09)

  • Page 74: Power Supply Diagram

    Supply 3.3V LAN8720 24-QFN VDDCR VDD1A VDDIO VDD2A BYPASS RBIAS nRST 49.9 Resistors Magnetic Supply 2.5 - 3.3V Magnetics BYPASS Figure 8.5 Copper Interface Diagram DATASHEET Datasheet Power to magnetics interface. BYPASS BYPASS RJ45 1000 pF 3 kV SMSC LAN8720/LAN8720i...

  • Page 75: Magnetics Selection

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Magnetics Selection For a list of magnetics selected to operate with the SMSC LAN8720, please refer to the Application note “AN 8-13 Suggested Magnetics”. http://www.smsc.com/main/appnotes.html#Ethernet%20Products SMSC LAN8720/LAN8720i DATASHEET Revision 1.0 (05-28-09)

  • Page 76: Chapter 9 Package Outline

    DATASHEET Datasheet REMARKS Overall Package Height Standoff Mold Thickness X Overall Size X Mold Cap Size X exposed Pad Size Y Overall Size Y Mold Cap Size Y exposed Pad Size Terminal Length Terminal Pitch Terminal Width Coplanarity SMSC LAN8720/LAN8720i...

  • Page 77: Figure 9.1 Qfn, 4X4 Taping Dimensions And Part Orientation

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation SMSC LAN8720/LAN8720i Revision 1.0 (05-28-09) DATASHEET...

  • Page 78: Figure 9.2 Reel Dimensions

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 9.2 Reel Dimensions Note: Standard reel size is 4000 pieces per reel. Revision 1.0 (05-28-09) SMSC LAN8720/LAN8720i DATASHEET...

  • Page 79: Chapter 10 Revision History

    Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 10 Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.0 (05-28-09) Rev. 1.0 Initial Release (04-15-09) SMSC LAN8720/LAN8720i Table 10.1 Customer Revision History Revised LAN8720 ordering information. DATASHEET CORRECTION Revision 1.0 (05-28-09)

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