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Komodo CXP Reference Guide
(Part-No. KY-FGK)
2 0 a M e s i l a S t . , N e s h e r 3 6 8 8 5 2 0 , I s r a e l
July 2018
P O B 2 5 0 0 4 , H a i f a 3 1 2 5 0 0 1 , I s r a e l
T e l : ( + 9 7 2 ) - 7 2 - 2 7 2 3 5 0 0 F a x : ( + 9 7 2 ) - 7 2 - 2 7 2 3 5 1 1
w w w . k a y a i n s t r u m e n t s . c o m
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Table of Contents
Related Manuals for Kaya Instruments KY-FGK
Summary of Contents for Kaya Instruments KY-FGK
- Page 1 Komodo CXP Reference Guide (Part-No. KY-FGK) 2 0 a M e s i l a S t . , N e s h e r 3 6 8 8 5 2 0 , I s r a e l July 2018...
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Page 2: Table Of Contents
Contents Figures and Tables ......................3 Introduction ......................... 5 Safety Precautions ....................5 Disclaimer ......................6 Key Features ........................7 Overview ....................... 7 Features ......................... 7 Product Applications ..................... 8 Related documents and accessories ............... 8 Ordering Codes……………………......………………….……..9 Board Components ......................10 Board component Blocks .................. - Page 3 Contents Absolute maximum ratings ................... 36 Electrical Characteristics..................... 37 Power Supply ......................37 Maximum and minimum input voltages ............... 37 Power rails ......................37 Electrical characteristics for board IO’s: ............... 38 Absolute maximum ratings for GPIO ..............40 Available Configurations ....................41 Available Configurations ..................
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Page 4: Figures And Tables
Figures and Tables Figures 1: B ........................ 11 IGURE OARD BLOCK DIAGRAM 2: K ......................11 IGURE OMODO FRONT VIEW 3: JTAG .......................... 13 IGURE CONNECTOR 4: FLASH ........................13 IGURE CONNECTOR 5: C ............14 IGURE LOCKS PIN ASSIGNMENTS SIGNAL NAME AND FUNCTIONS 6: I/O ...................... - Page 5 Figures and Tables 12: A ..................... 36 ABLE BSOLUTE MAXIMUM RATINGS 13: P ..........................37 ABLE OWER INPUT 14: M .............. 37 ABLE AXIMUM AND MINIMUM INPUT VOLTAGES FROM 15: P ................38 ABLE OWER RAILS ON THE OMODO BOARD 16: LVDS O ) .............
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Page 6: Introduction
Introduction Safety Precautions With your Komodo CXP in hand, please take a minute to read carefully the precautions listed below in order to prevent unnecessary injuries to you or other personnel or cause damage to property. Before using the product, read these safety precautions carefully to assure correct use. -
Page 7: Disclaimer
Otherwise, the product may be damaged. Disclaimer Even if the product is used properly, KAYA Instruments assumes no responsibility for any damages caused by the following: - Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts caused by a third party or other accidents, the customer’s willful or... -
Page 8: Key Features
Key Features Overview Komodo CXP is high-performance yet low-cost FPGA card supporting up to 8 CoaXPress standard interfaces. Each link supports standard CoaXPress bitrate of up to 6.25 Gbps. The card is based on Arria V GZ powerful FPGA that offers up to 400K flexible logic elements, 1K DSP blocks and 28Mbit of embedded memory. -
Page 9: Product Applications
Key Features 4 LVDS inputs 4 LVDS outputs 8 opto-isolated outputs 8 opto-isolated inputs Transfer Rate of up to 60 Gbps through PCIe Transfer Rate of up to 50 Gbps (8 x 6.25 Gbps) through the CoaXPress interfaces ... -
Page 10: Ordering Codes
Key Features Ordering Codes KY-FGK- 0: 16 Gb 1: 48 Gb 2: 80 Gb 0 - 8 3: 144Gb Notes: 1. Maximum of Receiver and Transmitter channels together is 8 2. Custom models available on request Komodo CXP Reference Guide... -
Page 11: Board Components
Board Components Board component Blocks One Arria V GZ 5AGZME5HF35C4 FPGA in an 1152-pin BGA (FBGA) 400K LEs 1092 DSP blocks 28 Mbit on-die block memory 3276 9x9 multipliers 2184 18x18 multipliers 1092 27x27 multipliers ... -
Page 12: Board Block Diagram
Board Components Board Block diagram GPIO 4 green user EPCQ Flash LEDs Equalizer/Driver DIN connector 1 JTAG Bank A DDR3 ×64 16 Gb Bank B Equalizer/Driver DIN connector 8 SODIMM DDR3 ×64 up to 128 Gb 8 dual color Oscillators LEDs PCIe 3.0 ×8... -
Page 13: Komodo Cxp Board Components
Board Components Komodo CXP Board components Board reference Type Description FPGA FPGA Arria V GZ 5AGZME5HF35, 1152-pin FBGA Configuration, Status and setup elements JTAG header Provide access to the JTAG chain EPCQ programming Provide access to the EPCQ using Active Serial header protocol Located on a daughter board above the DIN... -
Page 14: 4.6.1 Fpga Configuration Via Jtag
Board Components 4.6.1 FPGA configuration via JTAG The JTAG programming header provides a method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster connects to the board through standard Altera JTAG header (J3). Figure 3: JTAG connector 4.6.2 FPGA configuration via on board flash memory The Komodo CXP has an on board EPCQ256 flash memory. -
Page 15: Clocking
Board Components Clocking The Komodo CXP has a variety of on board oscillators, as described in the table and figure below: 25 MHz clk25[1] Oscillator 100 MHz pcie_refclk_p/n From PCIe edge cxp_clkp/n connector 125 MHz Oscillator 25 MHz clk25[0] Oscillator Figure 5: Clocks pin assignments, signal name and functions Arria V Arria V... -
Page 16: I/O And Transceivers
Board Components I/O and Transceivers The Komodo CXP utilizes several I/O banks out of the possible 26 I\O or transceiver banks available on the Arria V GZ FPGA. The following figure describes what each bank is used for: DDR3 SODIMM CoaXPress transceirers PCIe_Rx... -
Page 17: General Purpose I\O
Board Components 4.8.1 General purpose I\O The Komodo CXP supports 40 different I\O connections (on the FPGA), as described in the figure and table below: Figure 7: General purpose Inputs and outputs Komodo CXP Reference Guide... -
Page 18: Table 3: General Purpose
Board Components Arria V Board Signal Name GZ Pin I/O Standard Description reference (J1) Number Pin 1 of this header is the positive signal and pin 2 in the negative rout[0] AH26 3.3-V LVTTL signal of this LVDS. The differential pair is converted to a single input on the FPGA Pin 3 of this header is the positive signal and pin 4 in the negative... -
Page 19: Table 4: General Purpose
Board Components Arria V Board Signal Name GZ Pin I/O Standard Description reference (J2) Number Pin 1 of this header is the positive signal and pin 2 in the negative rout[2] AJ27 3.3-V LVTTL signal of this LVDS. The differential pair is converted to a single input on the FPGA Pin 3 of this header is the positive signal and pin 4 in the negative... -
Page 20: 4.8.2 General Purpose Leds
Board Components The “diff_en[0]” signal coming from the FPGA (pin AL25), enables (when set to logic 1) data transfer from pins 1 - 4 on the GPIO header, to pins AH26 and AK28 on the FPGA. This signal also enables data transfer from pins AK27 and AM26 on the FPGA to pins 5 – 8 on the GPIO header. The “diff_en[1]”... -
Page 21: Pci Express (Gen 3.0)
Board Components PCI Express (Gen 3.0) The Komodo CXP is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1) or 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2) or 8.0 Gbps/lane for a maximum of 64 Gbps full-duplex (Gen3). -
Page 22: Memory
Board Components pcie_tx_p[5] 1.5-V PCML pcie_tx_n[5] 1.5-V PCML pcie_tx_p[6] 1.5-V PCML pcie_tx_n[6] 1.5-V PCML pcie_tx_p[7] 1.5-V PCML pcie_tx_n[7] 1.5-V PCML pcie_rx_p[0] AL33 1.5-V PCML pcie_rx_n[0] AL34 1.5-V PCML pcie_rx_p[1] AJ33 1.5-V PCML pcie_rx_n[1] AJ34 1.5-V PCML pcie_rx_p[2] AG33 1.5-V PCML pcie_rx_n[2] AG34 1.5-V PCML... -
Page 23: Figure 9: Rzq
Board Components SODIMM DDR3 DDR3 IP on-board DDR3 Figure 9: RZQ connection when only the on-board memory is used If only the SODIMM DDR3 memory is used, this signal should be connected to the DDR3 IP that controls this memory, as shown in the following figure: SODIMM DDR3 DDR3 IP on-board DDR3... -
Page 24: 4.10.1 On-Board 16Gb Ddr3
Board Components SODIMM DDR3 SODIMM DDR3 DDR3 IP DDR3 IP (Slave) (Master) sharing sharing enabled enabled DDR3 IP DDR3 IP (Master) (Slave) on-board DDR3 on-board DDR3 Figure 11: RZQ connection when both memories are used 4.10.1 On-Board 16Gb DDR3 The Komodo CXP supports four, 32Mx16x8 bank, DDR3 SDRAM interface for very high-speed sequential memory access. -
Page 25: Figure 12: O N - Board Ddr3
Board Components The four x16 devices share some of the control signals, in the following table and figure those signals are shown: FPGA DDR3 IP common address data [15:8] and and control signals data [55:48] signals data [39:32] and data [7:0] and data [63:56] signals data [31:24] signals DDR3... - Page 26 Board Components ddr3_2_ba[2] AA15 1.35-V SSTL ddr3_2_cke 1.35-V SSTL Clock enable ddr3_2_clk_p AE14 Differential 1.35-V SSTL Differential clock input ddr3_2_clk_n AE13 Differential 1.35-V SSTL ddr3_2_csn AH15 1.35-V SSTL Chip select ddr3_2_wen AD14 1.35-V SSTL Write enable ddr3_2_rasn AB15 1.35-V SSTL Row address select ddr3_2_casn AA12...
- Page 27 Board Components ddr3_2_dq[42] AM22 1.35-V SSTL ddr3_2_dq[43] AM20 1.35-V SSTL ddr3_2_dq[44] AP22 1.35-V SSTL ddr3_2_dq[45] AM19 1.35-V SSTL ddr3_2_dq[46] AK21 1.35-V SSTL ddr3_2_dq[47] AP21 1.35-V SSTL ddr3_2_dqs_p[2] AK17 Differential 1.35-V SSTL Data strobe P byte lane 0 ddr3_2_dqs_n[2] AK18 Differential 1.35-V SSTL Data strobe N byte lane 0 ddr3_2_dqs_p[5] AN19...
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Page 28: Optional Sodimm (Up To 128Gb)
Board Components ddr3_2_dq[51] 1.35-V SSTL ddr3_2_dq[52] 1.35-V SSTL ddr3_2_dq[53] AD23 1.35-V SSTL ddr3_2_dq[54] 1.35-V SSTL ddr3_2_dq[55] AA22 1.35-V SSTL ddr3_2_dqs_p[1] AC20 Differential 1.35-V SSTL Data strobe P byte lane 0 ddr3_2_dqs_n[1] AC21 Differential 1.35-V SSTL Data strobe N byte lane 0 ddr3_2_dqs_p[6] AB21 Differential 1.35-V SSTL... - Page 29 Board Components ddr3_1_clk_p[1] Differential 1.35-V SSTL Differential clock input 1 ddr3_1_clk_n[1] Differential 1.35-V SSTL ddr3_1_csn[0] 1.35-V SSTL Chip select 0 ddr3_1_csn[1] 1.35-V SSTL Chip select 1 ddr3_1_wen 1.35-V SSTL Write enable ddr3_1_rasn 1.35-V SSTL Row address select ddr3_1_casn 1.35-V SSTL Column address select ddr3_1_resetn 1.35-V SSTL...
- Page 30 Board Components ddr3_1_dq[29] 1.35-V SSTL ddr3_1_dq[30] 1.35-V SSTL ddr3_1_dq[31] 1.35-V SSTL ddr3_1_dq[32] 1.35-V SSTL ddr3_1_dq[33] 1.35-V SSTL ddr3_1_dq[34] 1.35-V SSTL ddr3_1_dq[35] 1.35-V SSTL ddr3_1_dq[36] 1.35-V SSTL ddr3_1_dq[37] 1.35-V SSTL ddr3_1_dq[38] 1.35-V SSTL ddr3_1_dq[39] 1.35-V SSTL ddr3_1_dq[40] 1.35-V SSTL ddr3_1_dq[41] 1.35-V SSTL ddr3_1_dq[42] 1.35-V SSTL ddr3_1_dq[43]...
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Page 31: Coaxpress Interface
Board Components ddr3_1_dqs_p[6] Differential 1.35-V SSTL Data strobe P byte 6 ddr3_1_dqs_n[6] Differential 1.35-V SSTL Data strobe N byte 6 ddr3_1_dqs_p[7] Differential 1.35-V SSTL Data strobe P byte 7 ddr3_1_dqs_n[7] Differential 1.35-V SSTL Data strobe N byte 7 Clock connection for sodimm_scl AC24 3.3-V LVTTL... - Page 32 Board Components LVTTL output voltage has reached 90% of the full 24V If PoCXP is enabled, this signal indicates current limit 3.3-V cxp_flagb[2] or under voltage or over temperature state (of the over LVTTL current protection load switch) 1.5V PCML High Speed Data In, positive SDOp[2] 1.5V PCML...
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Page 33: Table 9: Coa Xp
Board Components 3.3-V If PoCXP is enabled, this signal indicates that the pwrg[6] AK23 LVTTL output voltage has reached 90% of the full 24V If PoCXP is enabled, this signal indicates current limit 3.3-V cxp_flagb[6] or under voltage or over temperature state (of the over LVTTL current protection load switch) 1.5V PCML... -
Page 34: Figure 13: Rx Channel Connection To The Equalizer
Board Components The following figure describes the Rx connection of the equalizer to the DIN connector. Figure 13: Rx channel connection to the equalizer The following figure describes the Tx connection of the driver to the DIN connector. Figure 14: Tx channel connection to the driver Komodo CXP Reference Guide... -
Page 35: Figure 15: Dedicated Coa
Board Components Near each DIN connector (on the dedicated daughter board, above the DIN connectors) there is a dual-color LED intended for showing the CoaXPress status of each link: Board Signal Arria V GZ I/O Standard Description reference Name Pin Number led_g[0] 2.5 V (Open drain) led_r[0]... -
Page 36: Fan Control (J6)
Board Components Fan Control (J6) The fan that is connected to the heat-sink above the FPGA can be controlled with a dedicated I/O, as described in the following table: Board Signal Arria V GZ Description reference (J6) Name Pin Number Standard User controlled fan output. -
Page 37: Mechanical Specifications
The Komodo CXP is a half-length, full-height, PCIe card according to PCI Express Card Electromechanical Specification, 109.81mm x 167.65mm. The exact board mechanical dimensions are as defined in Figure 17. For more detailed information please, contact KAYA Instruments representative. Figure 17: PCB Mechanical Dimensions Absolute maximum ratings... -
Page 38: Electrical Characteristics
Electrical Characteristics Power Supply The Komodo CXP board receives its power from the PCI express edge connector and external power supply directly from computer PSU using connector located on the right up side of the board (standard PC power connector). According to PCIe standard 3.0, the board might consume up to 10W of power, while actual power consumption depends on usage mode and interfaces. -
Page 39: Electrical Characteristics For Board Io's
Electrical Characteristics VCCA_GXBR1 VCCIO7A, VCCIO7B, VCCPD3CD, VCCPD4, VCCPD7, VCCPD8, VCCA_FPLL, VCC_AUX VCCPT, VCCPGM, VCCH_GXBL0, VCCH_GXBL1, VCCH_GXBR0, VCCH_GXBR1, VCCD_FPLL VCCIO3C, VCCIO3D, VCCIO4C, VCCIO4D, VCCIO7C, VCCIO7D, VDD, VDDQ (DDR3 SDRAM) 1.35 VCCIO8A, VCCIO8C, VCC (DDR3 SODIMM) VCCIO8D VCCR_GXBL0, VCCR_GXBL1, VCCR_GXBR0, VCCR_GXBR1, VCCT_GXBL0, VCCT_GXBL1, VCCT_GXBR0, VCCT_GXBR1 VCC, VCCHIP_L, VCCHSSI_L, 0.85... -
Page 40: Table 17: Lvds Input Dc Specifications (Receiver Inputs)
Electrical Characteristics Symbol Parameter Condition Units Differential Input High Threshold = 1.2 V, 0.05 V, 2.35 V Differential Input Low -100 Threshold Common-Mode Voltage = 100 mV, V = 3.3 V 0.05 Range = 3.6 V ±4 µA = 0 V or 2.8 V Input Current = 0 V ±1... -
Page 41: Absolute Maximum Ratings For Gpio
Electrical Characteristics Absolute maximum ratings for GPIO Specification Minimum voltage [V] Maximum voltage [V] LVDS -0.3 Opto-isolated (in) Opto-isolated (out) -0.5 LVTTL -0.5 Note: The maximum current that the Opto-isolated (out) IOs can support is 150mA Table 22: Absolute maximum ratings for GPIO Komodo CXP Reference Guide... -
Page 42: Available Configurations
The Komodo CXP board is available in various configurations depending on the number of cameras you want to connect as a Host or Device Links. Model Host Links Device Links KY-FGK-080 KY-FGK-400 KY-FGK-440 Table 23 : Available Configurations Link Number... -
Page 43: Top Level Example Design
Top Level Example Design The top level example design contains all the required project settings and an empty top level design for KOMODO CXP in Verilog and VHDL. The top level design files can be found under fpga_top_level folder in software CD. Komodo CXP Reference Guide... -
Page 44: Reference Design
Reference Design The reference design demonstrates the basic operation of all the board interfaces. The reference design is supplied in open source Verilog code. The reference design is located under fpga_reference_design folder in the software CD. The following interfaces are included: 1. -
Page 45: 9.1.1 Ddr3 Memories
The access to the PCIe from PC can be made using JINGO driver that should be downloaded separately from http://www.jungo.com/st/products/windriver/. KAYA instruments also offers PCI Express Gen3 x8 IP, High performance Scatter Gather DMA IP and a Drivers for DMA and PCI Express both for Windows and Linux. For IP licensing options please contact KAYA Instruments representative. -
Page 46: Using The Reference Design
Table 25 : IP Address The IP requires a license to compile. To install the license follow the guidelines below: 1. Save the “license.dat” file received from KAYA Instruments on the hard drive. 2. Open Quartus 3. For the web edition: Using “Tools->license Setup-> license file” choose the provided “license.dat”... -
Page 47: Board Diagnostic
To populate the external loopbacks a specific fixtures are required. Some of the fixtures are proprietary to KAYA Instruments. Please contact KAYA Instruments representative for availability of the fixtures. For DDR3 SODIMM test a MT8KTF51264HZ-1G6E1 SODIMM from Micron is required as shown in Figure 19. -
Page 48: Figure 20: Komodo Cxp
Reference Design The KOMODO CXP board with all the loopback fixtures connected can be seen in Figure 20. Figure 20: KOMODO CXP with JTAG connection To run the diagnostic follow the below steps: Make sure Quartus II is installed on your PC. ...