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JRC NJU6676 Manual
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JRC NJU6676 Manual

JRC NJU6676 Manual

64-common x 132-segment + 1-icon common bit map lcd driver
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64-common X 132-segment + 1-icon common
GENERAL DESCRIPTION
The NJU6676 is a bit map LCD driver to display
graphics or characters. It contains 8,580 bits display
data
RAM,
microprocessor
instruction decoder, 132-segment drivers, 64-common
drivers and 1-icon common driver.
The bit image display data is transferred to the
display data RAM by serial or 8-bit parallel interface.
65 x 132 dots graphics or 8-character 4-line by 16 x
16 dots character with icon are displayed by NJU6676
itself.
The wide operating voltage from 2.2 to 5.5V and low
operating current are useful for small size battery
operating items.
The build-in Electrical Variable Resistance is very
precision, furthermore the rectangle outlook is very
applicable to COG or Slim TCP.
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM - 8,580 bits
197 LCD Drivers - 64-common and 132-segment + 1-icon common
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface
Programmable Bias selection ; 1/7,1/9 bias
Useful Instruction Set
Display ON/OFF Cont, Display Start Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, ADC Select, Inverse Display, All On/Off, Bias Select, Read Modify Write,
End, Reset, Common Driver order Assignment, Power control set, Driver On/Off, EVR Mode Set,
EVR Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Saving.
Power Supply Circuits for LCD Incorporated
Voltage Booster Circuits (4-time Maximum), Regulator, Voltage Follower x 4
Precision Electrical Variable Resistance (64-step)
Low Power Consumption 80uA(Typ.).
Operating Voltage (All the voltages are based on VDD=0V.)
- Logic Operating Voltage
- Voltage Booster Operating Voltage : -2.5V ∼
- LCD Driving Voltage
Rectangle outlook for COG
Package Outline : Bump-chip
C-MOS Technology (Substrate : N)
Ver.2004-03-01
Bit Map LCD Driver
interface
circuits,
: -2.2V ∼ -5.5V
: -6.0V ∼ -18.0V
NJU6676
PACKAGE
NJU6676CL
- 1 -

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Summary of Contents for JRC NJU6676

  • Page 1 NJU6676 64-common X 132-segment + 1-icon common Bit Map LCD Driver GENERAL DESCRIPTION PACKAGE The NJU6676 is a bit map LCD driver to display graphics or characters. It contains 8,580 bits display data RAM, microprocessor interface circuits, instruction decoder, 132-segment drivers, 64-common drivers and 1-icon common driver.
  • Page 2 NJU6676 PAD LOCATION DUMMY4 DUMMY1 S131 OSC1 S130 OSC2 WR(R/W) RD(E) D6(SCL) D7(SI) VSS2 VSS2 VSS2 VSS2 VOUT VOUT Chip Center : X=0um, Y=0um Chip Size :X=8.72mm,Y=2.37mm Chip Thickness : 675um ± 30um Bump Size : 45um x 83um Bump Pitch : 60um(Min.)

  • Page 3: Pad Coordinates

    NJU6676 PAD COORDINATES Chip Size 8.72 x 2.37mm(Chip Center X=0um, Y=0um) PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um) DUMMY1 -4139 -1025 1655 -1025 OSC1 -3347 -1025 1715 -1025 OSC2 -3287 -1025 1775 -1025 -3129 -1025 1835 -1025...
  • Page 4 NJU6676 PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um) 4200 1533 1025 4200 1473 1025 4200 1413 1025 4200 1353 1025 4200 1293 1025 4200 1233 1025 4200 1173 1025 4200 1113 1025 COMM 4200 1053 1025 DUMMY3...
  • Page 5 NJU6676 PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um) -1467 1025 -4200 -1527 1025 -4200 -1587 1025 -4200 -1647 1025 -4200 -1707 1025 -4200 -1767 1025 -4200 -1827 1025 -4200 -1887 1025 -4200 -1947 1025 -4200 -2007 1025...

  • Page 6: Block Diagram

    NJU6676 BLOCK DIAGRAM C0 - - - - C31 C63 - - - - C32 S0 - - - - - - - - - - - - - S131 COMM Common Segment Drivers Common V1 to V5 Drivers Drivers...

  • Page 7: Terminal Description

    NJU6676 TERMINAL DESCRIPTION Symbol Description 1,76, DUMMY1~ Dummy Terminals. 110,243 DUMMY4 These are open terminals electrically. 11,17 VDD=+3V 26∼29 51,52 65∼67 73,75 8,14, VSS=0V 30,31, 32,49, 50,70,74 33∼36 VSS2 Reference voltage for voltage booster 53,54 LCD Driving Voltage Supplying Terminal. When the internal voltage booster...
  • Page 8 CLS=”L” : Internal oscillator circuit is disabled (requires external input) When CLS=”L”, input the display clock through the CL terminal. This terminal selects the master/slave operation for the NJU6676. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the LCD, synchronizing the LCD system.
  • Page 9 NJU6676 Symbol Description Display clock input/output terminal. The following is true depending on the M/S and CLS status. “H” Output “H” “L” Input “L” Input *:Don’t Care LCD alternating current signal I/O terminal. M/S = ”H” : Output M/S = ”L” : Input LCD Display blanking control terminal.
  • Page 10 NJU6676 Functional description (1) Block circuits description (1-1) Busy Flag (BF) During internal operation, the LSI is being busy and can’t accept any instructions except “status read”. The BF data is output through D7 terminal by the “status read” instruction.
  • Page 11 NJU6676 Fig.1 Display data RAM (DDRAM) Map Page Address Data Display Pattern Line Common Address Driver (00)H COM0 COM1 D3,D2,D1,D0 COM2 (0,0,0,0) Page 0 COM3 COM4 COM5 COM6 COM7 Initial COM8 COM9 D3,D2,D1,D0 COM10 (0,0,0,1) Page 1 COM11 COM12 COM13...
  • Page 12 NJU6676 (1-7) Common direction register The common direction register specifies common driver’s scanning direction. Table 1. Register Common drivers PAD No. Pin name COM0 COM31 COM63 COM32 COM63 COM32 COM0 COM31 (1-8) Reset circuit The reset circuit initializes the LSI to the following status by using of the reset signal into the RES terminal.
  • Page 13 NJU6676 b) Display data latch circuit The display data latch circuit temporally stores 132-bit display data transferred from the DDRAM in the synchronization with the common timing signal, and then it transfers these stored data to the segment drivers. “Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the contents of this latch circuit, they can’t change the contents of the DDRAM.
  • Page 14 NJU6676 f) Oscillator This is the low power consumption CR oscillator which provides the display clock and voltage converter timing clock. g) Internal power circuits The internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step EVR and voltage followers.
  • Page 15 NJU6676 - Power Supply applications Power Control Instruction D2 : Boost Circuit D1 : Voltage Regulator D0 : Voltage Follower 1) Internal power supply Example. 2) Only V Supply from outside Example. All of the Internal Booster, Voltage Regulator, Internal Voltage Regulator, Voltage Follower using.
  • Page 16 NJU6676 (2) Instruction set The D7 to D0 data is distinguished as display data or instruction data by the combination of A0, RD and WR signals. Table.4 Instruction table Instruction Instruction code Description Display On/Off 0 :Off 1 :On Initial display line set...
  • Page 17 NJU6676 (2-1) Instruction description (a) Display On/Off This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM. Display On or Off 0 :Off 1 :On (b) Initial display line set This instruction specifies the DDRAM line address which corresponds to the COM0 position.
  • Page 18 NJU6676 (d) Column address set As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute both “page address set” and “column address set” before accessing. The 8-bit column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column address register.
  • Page 19 NJU6676 (g) Display data read This instruction reads out the display data stored in the selected column address on the DDRAM. The column address automatically increments (+1) whenever the display data is read out by this instruction, so that this instruction can be continuously issued without “column address set”...
  • Page 20 NJU6676 (l) Read modify write This instruction controls column address increment. By using of this instruction, the column address can’t increment when read operation but it can increment when write operation. This status will be continued until the below-mentioned “end”...
  • Page 21 NJU6676 (m) End The “end” instruction cancels the read modify write mode and makes the column address return to the initial value just before “read modify write” is started. Return Column Address Read modify write (n) Reset This instruction reset the LSI to the following status, however it doesn’t change the contents of the DDRAM.
  • Page 22 This instruction controls LCD driving waveform output through the COM/SEG terminals. Driver The NJU6676 contains low power LCD driving voltage generator circuit reducing own operating current. Therefore , it requires the following sequence procedures at power on for power source stabilized operation.
  • Page 23 NJU6676 (r) EVR set 1) EVR mode set This instruction sets the LSI into the EVR mode, and it is always used by the combination with “EVR register set”. The LSI can’t accept any instructions except the “EVR register set” during the EVR set mode. This mode will be released after the “EVR register set”...
  • Page 24 NJU6676 (t) Power save mode On/Off This instruction sets the LSI into the power save mode by the combination of “display off” and “entire display on” instructions for reducing operating current as well as static operation’s. The internal status and the contents of the DDRAM will be remained just before the “power save mode on/off”...
  • Page 25 NJU6676 (3) Internal power circuits (3-1)Voltage converter The voltage converter generates maximum 4x boosted negative-voltage from the voltage between VDD and Vss2. The boosted voltage is output from the VOUT terminal. The internal oscillator is required to be operating when using this converter, because the divided signal provided from the oscillator is used for the internal timing of this circuit.
  • Page 26 NJU6676 (3-2)Contrast control using the voltage regulator The voltage regulator determines the LCD driving voltage “V5” according to the Rb/Ra ratio and VREG voltage. The equations to calculate V5 are as follows: Voltage regulator VREG VLCD Vout Fig.3 Voltage regulator circuit VLCD = VDD –...
  • Page 27 NJU6676 - VLCD setting example We recommend the total value of Ra and Rb is between 1MΩ and 5MΩ. When using Ra=1MΩ, Rb=3MΩ and VDD=3V, the VLCD is calculated as follows: The minimum VLCD: VLCD =(1+Rb/Ra) X VREG =(1+3/1) X [(99/162) X 3.0] =7.33V...
  • Page 28 NJU6676 (3-4) LCD Driving Voltage Generation Circuits The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the VLCD (VLCD=VDD-V5) voltage with the internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with voltage follower circuit.
  • Page 29 (4-1) Interface type selection NJU6676 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or serial interface is determined by a condition of the P/S terminal connecting to "H" or "L"...
  • Page 30 A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L" or CS1 terminal becomes "H" before 8th serial clock rise edge, NJU6676 recognizes them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart for the serial interface is shown in Fig.
  • Page 31 (4-4) Access to the Display Data RAM and Internal Register. The NJU6676 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between MPU and the Display Data RAM or Internal Register.
  • Page 32 NJU6676 (4-5) Chip select CS1, CS2 are Chip Select terminals. In case of CS1="L" and CS2=”H”, the interface with MPU is available. In case of CS1=”H” or CS2=”L”, the D0 to D7 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is selected when CS1=”H” or CS2=”L”, the shift register and the counter are reset.
  • Page 33 In case of inputting external LCD driving voltage, LCD drive voltage should start supplying to NJU6676 at the mean time of turning on VDD power supply or after turned on VDD. In use of the voltage boost circuit, the condition that the supply voltage : 18V >VDD-Vout is necessary.
  • Page 34 REG% VDD=3V, Ta=25°C Note5) Although the NJU6676 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with MPU. Note6) RON is the resistance values in supplying 0.1V voltage-difference between power supply terminals (V1,V2,V3,V4) and each output terminals (common / segment).
  • Page 35 NJU6676 Power Control Operating Condition External Symbol Voltage Supply Voltage Voltage Voltage (Input Terminal) converter regulator followers IDD1 Use(V IDD2 Use(V IDD3 Use(V ∼V IDD4 Use(V Ver.2004-03-01 - 35 -...
  • Page 36 NJU6676 IDD 1,2,3,4 measurement circuits: IDD1 NJU6676 Vout IDD2 NJU6676 Vout IDD3 NJU6676 Vout IDD4 V1 V2 V3 V4 NJU6676 Vout Ver.2004-03-01 - 36 -...
  • Page 37 NJU6676 BUS TIMING CHARACTERISTICS Read and Write characteristics (80 type MPU) tcyc8 A0,CS1,CS2 tAW8 tAH8 tCCL tCCH WR,RD tDS8 tDH8 D7 to D0 Write tACC8 tOH8 D7 to D0 Read (Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min.
  • Page 38 NJU6676 (Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min. Max. Unit Address hold time A0,CS1, tAH8 Address set up time tAW8 System cycle time tcyc8 Control “L” pulse width (Write) tCCLW WR,RD Control “L” pulse width (Read) tCCLR Control “H”...
  • Page 39 NJU6676 Read and Write characteristics (68 type MPU) tcyc6 tEWL tAW6 tEW(H[R/W]･L[R/W]) tAH6 A0,CS1,CS2 tDS6 tDH6 D7 to D0 Write tOH6 tACC6 D7 to D0 Read (Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min. Max. Unit...
  • Page 40 NJU6676 (Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min. Max. Unit Address hold time tAH6 A0,CS1, Address set up time tAW6 System cycle time tcyc6 Enable “H” pulse width (Read) tEWHR Enable “H” pulse width (Write) tEWHW Enable “L”...
  • Page 41 NJU6676 Write characteristics (Serial interface) tCSS tCSH CS1,CS2 tSAS tSAH tscyc tSLW tSHW tSDS tSDH (Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min. Max. Unit Serial clock cycle tscyc SCL “H” pulse width tSHW SCL “L” pulse width...
  • Page 42 NJU6676 (Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C) Parameter Terminal Symbol Condition Min. Max. Unit Serial clock cycle tscyc SCL “H” pulse width tSHW SCL “L” pulse width tSLW Address set up time tSAS Address hold time tSAH Data set up time...
  • Page 43 NJU6676 Display control timing characteristics (OUT) tDFR =0V, V =4.5~5.5V, Ta=-30~80°C) Parameter Symbol Condition Min. Typ. Max. Unit Terminal FR Delay Time CL=50pF =0V, V =2.7~4.5V, Ta=-30~80°C) Parameter Symbol Condition Min. Typ. Max. Unit Terminal FR Delay Time CL=50pF =0V, V =2.2~2.7V, Ta=-30~80°C)
  • Page 44 NJU6676 LCD DRIVING WAVEFORM 64 65 2 3 4 -SEG -SEG Ver.2004-03-01 - 44 -...

  • Page 45: Application Circuit

    NJU6676 APPLICATION CIRCUIT (1) Microprocessor Interface Example The NJU6676 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU. * : C86 terminal must be fixed VDD or VSS. 80 Type MPU A1∼A7...
  • Page 46 NJU6676 (2) 65 x 264 dots Driving Application Circuits Example (Common and Segment Drivers Extension by using two of NJU6676) LCD Panel : 65 x 264 NJU6676 NJU6676 Master Slave [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions.
  • Page 47 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJU6676CL-G-CT2 NJU6676H01...

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