Example Of A Scatter-Gather Dma Operation For Rfm-5565 - GE PCIE-5565PIORC* Hardware Reference Manual

3.5 Example of a Scatter-Gather DMA Operation for RFM-5565

62 PCIE-5565PIORC Reflective Memory Board
Scatter‐Gather DMA transfer is a mode usually used to perform large data
transfers separated into multiple smaller pages or blocks. Note that a data page
must not cross a 4 GByte address boundary. The DMA descriptor pointer is the
address for a chained list of page descriptors.
Each page descriptor defines the address and size of a data block plus a pointer to
the next descriptor block. The descriptors are automatically fetched when needed
and then data is read/written to the corresponding page. The descriptor chain is
processed until the data transfer is finished or the end of the descriptor chain is
reached, whichever comes first.
Page descriptor blocks cannot be mapped in 64‐bit addressing space. The first
descriptor must be on a 16‐byte boundary. For best performance, each descriptor
block should be aligned on a 16‐byte or 8‐byte boundary.
A descriptor chain must be created in PCI 32‐bit memory space before starting a
Scatter‐Gather DMA. Each descriptor in the chain has this format:
1st Dword: Lower 32‐bit PCI Address for Data (each page must be aligned
on an 8‐byte boundary),
2nd Dword: Upper 32‐bit PCI Address for Data ($0 for 32‐bit addressing),
3rd Dword: Number of bytes to transfer to/from PCI Address (each page
size must be a multiple of 8 bytes),
4th Dword: PCI Address of Next Descriptor (write $1 in this field to denote
end of chain)
Also, keep a total for the size of all data blocks pointed to by the chain. This total
length value must be written to the DMA transfer size register.
1. Base Address Register 0 stores the starting address of the Local Control and
Configuration registers, which include the DMA Control registers. The value
in this register is PCIBAR0.
2. There are six DMA registers that must be configured to set up the DMA
cycle. These registers will remain unchanged after the DMA cycle.