Table 3-34 Link Status Register Bit Definition - GE PCIE-5565PIORC* Hardware Reference Manual

42 PCIE-5565PIORC Reflective Memory Board

Table 3-34 Link Status Register Bit Definition

Bit(s) Field
15:13 Reserved
12 Slot Clock
Configuration
11 Link Training
10 Link Training Error
9:4 Negotiated Link Width - 000001 = x1
3:0 Link Speed
Link Status Register Bit Definition: Offset 0x092
Description
Hardwired to 0x00
1 = The card uses the reference clock provided on the
connector
1 = Link Training in process
0 = Link Training done
1 = Link Training Error Occurred
0 = Link Successfully Trained
- 000010 = x2
- 000100 = x4
0001 (2.5 Gb/s)
R/W
R
R
R
R
R
R