Korg Poly-61 Service Manual page 19

PIN DESCRIPTION
Designation
Pin #
Function
Designation
Pin #
Vss
20
Circuit GND potential
RD 8
26
+5V during operation. Low power
standby pin.
VCc
40
Main power supply: +5V during
operation.
PROG
25
Output strobe for 8243 I/O
expander.
RESET 4
P10-P17
Port 1
27-34
8-bit quasi-bidirectional port.
P20-P27
21-24
8-bit quasi-bidirectional port.
WR
10
Port 2
35-38
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243
ALE 11
D0-D7 12-19
True bidirectional port which can
BUS
be written or read synchronously
using the RD, WR strobes. The
Port can also be statically latched.
Contains the 8 low order program
counter bits during an external
PSEN
9
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
SS
5
TO
1
Input pin testable using the con¬
ditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO CLK
instruction.
EA
7
T1
39
Input pin testable using the JT1,
and JNT1 instructions. Can be des¬
ignated the timer/counter input using
the STRT CNT instruction.
XTAL1 2
INT
6
Interrupt input. Initiates an inter¬
rupt if interrupt is enabled. Inter-
XTAL2
3
rupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the BUS from an external
device.
Used as a Read Strobe to External
Data Memory. (Active low)
Input which is used to initialize the
processor. Also used during verifi¬
cation, and power down. (Active
low) (Non TTL V||-|)
Output strobe during a BUS write.
(Active low)
Used as write strobe to External
Data Memory.
Address Latch Enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and pro¬
gram memory.
Program Store Enable. This output
occurs only during a fetch to exter¬
nal program memory. (Active low)
Single step input can be used in con¬
junction with ALE to "single step"
the processor through each in¬
struction. (Active low)
External Access input which forces
all program memory fetches to re¬
ference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
One side of crystal input for inter¬
nal oscillator. Also input for exter¬
nal source. (Not TTL Compatible)
Other side of crystal input.
1C M58981P-45 4096-BIT (1024-WORD BY 4-BIT) CMOS STATIC RAM
PIN CONFIGURATION
BLOCK DIAGRAM
ADDRESS
INPUTS
Vcc (5V)
GND (OV)
DATA
INPUT/
OUTPUT