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SingMai Electronics Multi-standard Video Encoder with cross-colour reduction User Manual Revision 0.3 June 2018 PT9 User Manual Revision 0.3 Page 1 of 38...
Date Revisions Version 19-11-2015 First draft. 29-08-2017 Revisions to comb filter. Cross-colour reduction description added. Pre-emphasis added. Cross luma reduction removed. Additions to technical description. 09-06-2018 Minor correction to Table 8. PT9 User Manual Revision 0.3 Page 2 of 38...
Interfacing to a DAC ........................27 Specification ..........................28 Measurements .......................... 29 Tables Table 1 PT9 Altera FPGA resource requirements ................... 5 Table 2 PT9 module heirachy........................6 Table 3 Input/Output signals ........................7 Table 4 BT656 Signal Levels ........................9 Table 5 BT656 test waveform (525 line) ....................
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Figure 10 Zone plate image after line comb decoding................ 16 Figure 11 Zone plate image after frame comb decoding..............17 Figure 12 Zone plate image, line comb decoded from PT9 encoder........... 18 Figure 13 NTSC zone plate with line comb decoder. Left: conventional encoder/line comb decoder.
27MHz, which can be used to directly drive a digital to analogue converter, modulator or other output device. PT9 includes special cross-colour reduction circuitry, particularly of help in reducing artifacts when used with a line comb video decoder. The encoder can also be set to a free-run mode in which it ignores the BT656 timing information and data and uses the clock input to generate a black and burst output.
SingMai Electronics 2. PT9 Module description The PT9 encoder comprises 10 Verilog modules. PT9_encoder.v is the top level module of the hierarchy; six of the other modules are instantiated from it. Top level level level level PT9_Register_control.v PT9_BT656_receiver.v PT9_SPG.v PT9_encoder.v PT9_Subcarrier_gen.v...
SingMai Electronics 3. Signal Interconnections The PT9 signal interconnect diagram is shown in Figure 1. Figure 1 PT9 Interconnection diagram. The signal descriptions are shown in Table 3, below. Signal Description Clock 27MHz clock input synchronous with the BT656 input data. The BT656 data should be stable at the rising edge of this clock.
Green Magenta Blue Black Table 4 BT656 Signal Levels The resulting nominal output levels for a 100% PAL colour bar input are shown in Figure 2. Figure 2 CVBS output levels PT9 User Manual Revision 0.3 Page 9 of 38...
SingMai Electronics 5. Test signals The PT9 is supplied with BT656 test waveforms to facilitate testing and verification. The waveforms are supplied as Excel spreadsheets and are 75% saturation colour bars. Other waveforms can be supplied on request for a small charge.
The top level module provides the interconnections to the other modules in the IP core. PT9_Register_control.v This module provides the register interface for the PT9. Chapter 8 provides a description of the interface and Chapter 9 provides a description of the registers.
The luminance signal is then passed to the comb filter module to provide the cross-colour reduction. A description of this mode can be found in Chapter 7. The luminance, chrominance and composite sync are then added together to generate the 10-bit 27MHz CVBS signal. PT9 User Manual Revision 0.3 Page 12 of 38...
The last block of the output-proc module is the pre-emphasis block. When driving long lengths of cable with the PT9 there will be a high frequency loss. This is usually compensated for with a high frequency boost network at the receiver (decoder). To provide better compensation the PT9 has a pre-emphasis filter that is matched to response of typical coaxial cable (e.g.
Chapter 7. The comb filter module also provides compensating delays for the chroma components. ram_infer_generic.v This module is a generic single port RAM that is used in the comb filter module. PT9 User Manual Revision 0.3 Page 14 of 38...
The chroma, once demodulated, will always contain high frequency luma. To reduce the interference of the chroma information for monochrome TV receivers, the chroma subcarrier frequency has a fixed phase relationship with respect to the horizontal line frequency. We can PT9 User Manual Revision 0.3 Page 15 of 38...
2D line comb decoder (where the comb taps are separated by a number of lines). This can be seen in the frame comb decoded image of the zone plate in Figure 11. PT9 User Manual Revision 0.3 Page 16 of 38...
Ideally the comb filter architectures for the encoder and decoder should be matched, which is the case for the SingMai PT9 encoder and the PT4 line comb decoder.
SingMai Electronics Figure 12 Zone plate image, line comb decoded from PT9 encoder. Figure 13 NTSC zone plate with line comb decoder. Left: conventional encoder/line comb decoder. Right: PT9 encoder with conventional line comb decoder. PT9 User Manual Revision 0.3...
PT9_WRn pulse. The address input also selects the register data that is presented on the PT9_Register_out[7:0] bus. This output is independent of the PT9_CSn or PT9_WRn inputs. Figure 14 Control interface Timing. PT9 User Manual Revision 0.3 Page 19 of 38...
Note that, if Control Register bit 7 is asserted (Auto register = ‘1’), then the default values for NTSC-M, PAL, PAL-M and PAL-N will be used by the PT9 and only the Control registers and the pre-emphasis register will be active.
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* 1/27MHz is the broad pulse width, nominally 27.3us. 11 bit value = (Broad1end2[2:0],Broad1end1[7:0]) Broad2 end 1 Width of the second broad pulse whose leading edge is Half line start. Increments of 1/27MHz. Maximum value = 1715 or 1727 PT9 User Manual Revision 0.3 Page 21 of 38...
Luma Scaling 2 10 bit value = (LumaScaling2[1:0],LumaScaling1[7:0]). CVBS gain 1 Composite video gain (used for matching to output stage). 9 bit value = (CVBSgain2[0],CVBSgain1[7:0]). CVBS gain 2 Table 7 Register descriptions PT9 User Manual Revision 0.3 Page 22 of 38...
SingMai Electronics 10. Horizontal timing registers Figures 15 and 16 show the timing specifications for NTSC and PAL-BG respectively. Figure 15 NTSC horizontal timing PT9 User Manual Revision 0.3 Page 23 of 38...
Note that, if Control Register bit 7 is asserted (Auto-register = ‘1’), then the hard-wired values will be used by PT9 depending on the video standard selected by Control Register 1, bits [5:4]. The hard-wired values are those shown in Table 8.
Y Pedestal only operates for NTSC-M and PAL-M Y Offset 1 Y Offset 2 Luma Scaling 1 Luma Scaling 2 CVBS gain 1 CVBS gain 2 Table 8 Default Register settings PT9 User Manual Revision 0.3 Page 26 of 38...
SingMai Electronics 12. Interfacing to a DAC The SM05 evaluation board provides a suitable platform to evaluate the performance of the PT9 encoder. The digital composite video output and the 27MHz clock can be used to directly drive a DAC – the SM05 board uses an ADI AD9706 12 bit DAC for this purpose. The output of the DAC is filtered and buffered.
SingMai Electronics 14. Measurements The PT9 multistandard encoder was measured using an SM05 evaluation board (with Altera EP4CE15 FPGA). The source was the PT6 video pattern generator IP core which provided the 10-bit BT656 input to the PT9 encoder. The composite digital output was converted to analogue using an Analog Devices AD9706 12 bit digital to analogue converter (top 10 bits driven).
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