Alarm Interrupt Airq; Countdown Timer Interrupt Tirq; Watchdog Timer Interrupt Wirq; Battery Low Interrupt Blirq - Micro crystal RV-1805-C3 Applications Manual

Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
4.13.2.

ALARM INTERRUPT AIRQ

The RV-1805-C3 may be configured to generate the AIRQ interrupt when the values in the Time and Date
Registers match the values in the Alarm Registers. Which register comparisons are required to generate AIRQ is
controlled by the ARPT field as described in TIMER REGISTERS, 18h - Countdown Timer Control, allowing
software to specify the interrupt interval. When an Alarm Interrupt is generated, the AF flag is set and an output
signal is generated based on the AIE bit and the pin configuration settings. The IM field controls the period of the
signal, including both level and pulse configurations.
4.13.3.

COUNTDOWN TIMER INTERRUPT TIRQ

The RV-1805-C3 may be configured to generate the TIRQ interrupt when the Countdown Timer is enabled by the
TE bit and reaches the value of zero, which will set the TF flag. The TM, TRPT and TFS fields control the interrupt
timing (see TIMER REGISTERS, 18h - Countdown Timer Control), and the TIE bit and the pin configuration
settings control the output signal generation.
4.13.4.

WATCHDOG TIMER INTERRUPT WIRQ

The RV-1805-C3 may be configured to generate the WIRQ interrupt when the Watchdog Timer reaches its timeout
value. This sets the WDF flag and is described in section WATCHDOG TIMER.
4.13.5.

BATTERY LOW INTERRUPT BLIRQ

The RV-1805-C3 may be configured to generate the BLIRQ when the voltage on the V
thresholds set by the BREF field. The polarity of the detected crossing is set by the BPOL bit.
4.13.6.

EXTERNAL INTERRUPT EIRQ

The RV-1805-C3 may be configured to generate the EIRQ interrupt when the WDI input toggles. The register bit
EIP control whether the rising or falling transitions generate the respective interrupt. Changing EIP may cause an
immediate interrupt, so the interrupt flag should be cleared after changing this bit.
The value of the WDI pin may be directly read in the WDIS bit (see RAM REGISTERS, 3Fh - Extension RAM
Address). By connecting the input such as a pushbutton to WDI, software can debounce the switch input using
software configurable delays.
4.13.7.

XT OSCILLATOR FAILURE INTERRUPT OFIRQ

The RV-1805-C3 may be configured to generate the OFIRQ interrupt if the XT oscillator fails (see XT
OSCILLATOR FAILURE DETECTION).
4.13.8.

AUTOCALIBRATION FAILURE INTERRUPT ACIRQ

The RV-1805-C3 may be configured to generate the ACIRQ interrupt if an Autocalibration operation fails (see
AUTOCALIBRATION FAIL).
RV-1805-C3
pin crosses one of the
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