Page 1 QN902x User Manual of QN902x Rev. 1.3 — 05 November 2018 User Manual Document information Info Content Keywords User manual, MCU, Register Abstract This document is a user manual of QN902x SoC.
Page 2 Added description on fast boot function. Removed description on QN902x temperature sensor. Contact information For more information, please visit: http://www.nxp.com UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 2 of 128...
Page 3: Introduction
Highly efficient ultra-low power operation  Excellent code density UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 3 of 128...
Page 4: Nested Vectored Interrupt Controller (Nvic)
Proprietary_RX SPI0_TX Proprietary_TX SPI0_RX BLE_RX UART1_TX BLE_TX UART1_RX BLE_FRQ_JUMP UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 4 of 128...
Page 5: Serial Wire Debug (Swd) Interface
Memory 6 : 1000c000 ~ 1000dfff Memory 7 : 1000e000 ~ 1000ffff UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 5 of 128...
Page 6: Reset Management Unit (Rmu)
Brown-out Detection (BOD)  RESET pin  Watchdog timeout reset UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 6 of 128...
Page 7: Register Description
Control analog peripherals 0BCh ADDITION Other analog internal control UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 7 of 128...
Page 8: Register Description
Write 1 to set datapath register reset RTC_RST Write 1 to set sleep timer reset UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 8 of 128...
Page 9 Write 1 to enable SPI AHB clock NGATING_GPIO Write 1 to enable GPIO clock UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 9 of 128...
Page 10 Write 1 to clear CPU reset Table 5 CMDCR (CLK_MUX_DIV_CTRL) Type Reset Symbol Description UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 10 of 128...
Page 11 ‘1’ is enable STCLKEN, so that SCLK of CPU can be gated by STCLKEN; 30-26 00000 RSVD Reserved UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 11 of 128...
Page 12 Please see GPIO MUX Table; Table 9 PMCR2 (PIN_MUX_CTRL2) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 12 of 128...
Page 13 SPI 1 Data in is connected with P2_0; Table 10 PDCR (PAD_DRV_CTRL) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 13 of 128...
Page 14 10b = Pull-up; 11b = Reserved Table 12 PPCR1 (PAD_PULL_CTRL1) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 14 of 128...
Page 15 10000000b = CPU software Reset; Table 14 IOWCR (IO_WAKEUP_CTRL) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 15 of 128...
Page 16 RADIO_EN BLE IP radio_en output; FREQ_WORD[7-0] BLE Frequency Word; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 16 of 128...
Page 17 2901h CHIP_ID[15-0] QN902X CHIP ID Table 18 PGCR0 (POWER_GATING_CTRL0) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 17 of 128...
Page 18 1 = Enable bond option; 0 = Disable bond option; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 18 of 128...
Page 19 1 = Switch off 32KHz XTAL power 0 = Switch on 32KHz XTAL power UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 19 of 128...
Page 20 1 = Switch off memory 1 power 0 = Switch on memory 1 power UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 20 of 128...
Page 21 0 = Disable CPU power down operation mode; DBGPMUENABLE Reserved UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 21 of 128...
Page 22 Reserved. Write ‘0’ 11-9 101b VT_PKDET1_HG[2-0] Reserved. Write ‘101b’ UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 22 of 128...
Page 23 1 = RX use VREG12_A, BUCK_TMOS and BUCK_BM, TX use VREG12_A_BAK,BUCK_TMOS_BAK,BUCK_BM_BAK; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 23 of 128...
Page 24 32.768KHz crystal bias current control IB = 25nA*X32ICTRL Table 23 XTAL_BUCK UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 24 of 128...
Page 25 Reserved. Write ‘0’ 29-26 0101b LO_TST_CP[3-0] Reserved. Write ‘0101b’ UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 25 of 128...
Page 26 ‘1’ is bypass ADC Divider; 0111b ADC_DIV[3-0] If ADC_DIV_BYPASS is ‘0’, UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 26 of 128...
Page 27 VDD) 1111b = Select internal reference voltage (15/16 VDD) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 27 of 128...
Page 28 1 is Enable P0_7/6 and P3_1/0 as Analog input ONLY. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 28 of 128...
Page 29 31-15 RSVE 14-12 000b BUCK_TMOS_BAK Write ‘111b’ 11-10 BUCK_BM_BAK UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 29 of 128...
Page 30 DIS_XPD_DLY Write ‘1’ PA_CKEN_SEL Write ‘1’ DC_CAL_MODE Write ‘0’ UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 30 of 128...
Page 31: Power Supply And Power Management Unit (Pmu)
DC-DC 1.8V Digital Analog Radio Figure 3 DC-DC Mode UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 31 of 128...
Page 32: Power Management Unit (Pmu)
It is the second lowest power state in the QN902x. This state is usually used between BLE connection or advertising events. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 32 of 128...
Page 33 Wakeup through external IO SLEEP Figure 5 Power Mode State Machine UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 33 of 128...
Page 34 Power gating control related registers are PGCR0, PGCR1, PGCR2, which are described in section 2.5.1. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 34 of 128...
Page 35: Analog-To-Digital Converter (Adc)
MHz or a 32 kHz clock, which is then divided according to the signal acquisition requirement before being applied to the ADC. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 35 of 128...
Page 36: Adc Input Stage
-6dB, 0dB, 6dB and 12dB by changing the register BUF_GAIN[1:0]. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 36 of 128...
Page 37: Adc Reference Voltage
ADC_EN to 1. The channel for conversion is selected by SCAN_CH_START[3:0]. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 37 of 128...
Page 38: Adc Output
ADC again before a new conversion. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 38 of 128...
Page 39: Register Description
0x06 = Reserved 0x07 = BATT (battery monitor) Others: Reserved UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 39 of 128...
Page 40 1= Hardware control, only working in single or single scan mode RSVD Reserved Table 29 ADC1 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 40 of 128...
Page 41 01b = 75% 10b = 100% 11b = 200% UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 41 of 128...
Page 42 0 = Disable 1 = Enable Table 30 ADC2 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 42 of 128...
Page 43: Software Document And Example Code
Refer to “QN902X API Programming Guide v1.0.pdf” and ADC example source code in the SDK. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 43 of 128...
Page 44 QN902x NXP Semiconductors User Manual of QN902x UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 44 of 128...
Page 45: Comparator
Output routed to multiple peripherals: Timer, INT Controller, Wakeup Source UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 45 of 128...
Page 46: Function Description
The input to the comparator positive pin is fixed to be from the input pin. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 46 of 128...
Page 47: Comparator Outputs
VDD) 0011b = Select internal reference voltage (3/16 VDD) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 47 of 128...
Page 48 VDD) 1110b = Select internal reference voltage (14/16 VDD) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 48 of 128...
Page 49 BLE deep sleep state. 1111b NC[3-0] No connected; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 49 of 128...
Page 50: Clock Management Unit (Cmu)
Figure 7 shows the block diagram of the Clock unit. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 50 of 128...
Page 51: Clock Sources
· 32/16 MHz crystal oscillator. · 20 MHz RC oscillator. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 51 of 128...
Page 52: Clock Description
The system clock can be sourced from the internal 20 MHz oscillator, from the 32MHz UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 53: Configure Apb Clock
CRSS is Enable clock gating and set block reset register, address is 0x40000000 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 54 DPREG_RST RTC_RST Write 1 to set sleep timer reset UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 54 of 128...
Page 55: Crsc
Write 1 to enable UART 0 clock NGATING_SPI_1 Write 1 to enable SPI 1 clock UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 55 of 128...
Page 56: Cmdcr
CMDCR is set clock switch and clock divider register, address is 0x40000008 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 57 ‘1’ is bypass APB Divider; APB_DIVIDER[1-0] If APB_DIV_BYPASS is ‘0’, UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 57 of 128...
Page 58: Stcr
Table 6 STCR. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 58 of 128...
Page 59: Inter-Integrated Circuit (I2C) Interface
The first byte of data transferred by the master immediately after the START signal is the UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 60: R/Nw Bit
The ACK/NACK bit is sent by the slave. After the master receives the ACK/NACK bit, UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 61: Master-Receive
START condition, slave address and R/nW bit. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 62: Slave-Transmit
NACK. All the transfer begins immediately after UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 62 of 128...
Page 63: Register Description
The I2C interface detected a 7-bit address on the bus that matches the pre-programmed SLAVE_ADDR[6:0]. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 63 of 128...
Page 64 Should match the R/nW bit. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 64 of 128...
Page 65 TX interrupt to indicate data transmitted. Write 1 to clear UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 65 of 128...
Page 66: Pwm
POL. When POL is set to 1, the output will be high when the counter is smaller than CMP. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 66 of 128...
Page 67: Register Description
PWM channel 0 interrupt enable: INT_EN_0 0 = disable; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 67 of 128...
Page 68 PWM channel 0 compare register. 15-8 CH0_CMP[7-0] PWM channel 0 period register. CH0_PERIOD[7-0] UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 68 of 128...
Page 69 1 = an interrupt pending. Write 1 to clear the interrupt. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 69 of 128...
Page 70: Real Time Clock (Rtc)
1LSB representing one second. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 70 of 128...
Page 71: Clock Accuracy Compensation
The other one represents the input capture interrupt. The status of the UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 72: Register Description
1 = enable Input capture enable CAP_EN 0 = disable UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 72 of 128...
Page 73 Control Register synchronization busy indicator CR_SYNC_BUSY 0 = Synchronization done; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 73 of 128...
Page 74 Second correction register. 31-15 SEC_CORR[16-0] RTC counter correction register. 14-0 CNT_CORR[14-0] UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 74 of 128...
Page 75 Reserved RTC counter current value, read only. 14-0 CNT_VAL[14-0] UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 75 of 128...
Page 76: Serial Peripheral Interface (Spi0/Spi1)
RX buffer, where it can be read from the RXD. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 76 of 128...
Page 77: Slave Mode Operation
In the master mode, the SCK is generated from the SPI_CLK as shown below: SCK=SPI_CLK/(2*(BITRATE[5:0]+1)) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 77 of 128...
Page 78: Tx/Rx Buffer
TX data register 014h RX data register 018h Status register UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 78 of 128...
Page 79: Register Description
1: high Table 55 CR1 Type Reset Symbol Description UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 79 of 128...
Page 80 0: RX buffer is not full 1: RX buffer is full UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 80 of 128...
Page 81 0: TX buffer is full 1: TX buffer is not full UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 81 of 128...
Page 82: Timers
That means that after QN902x reset, users need to configure register to make sure that the timer/counter work as required. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 82 of 128...
Page 83: Clock Sources
The PWM waveform can be generated upon the timer overflow or the compare match. The period and duty cycle can be programmed. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 83 of 128...
Page 84: Operation Modes
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 84 of 128...
Page 85: Input Capture Count Mode
Timer input capture/compare register 014h TCNT Timer counter current value register UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 85 of 128...
Page 86: Register Description
ICCLR 0 = positive edge; 1 = negative edge. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 86 of 128...
Page 87 Write 1 to clear the interrupt. Table 63 TOPR UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 87 of 128...
Page 88 In free-running mode, it’s used as compare register, setting by software; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 88 of 128...
Page 89 Read only. The bit-width of TCNT is same as Timer count; it can be 16 or 32 bits. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 89 of 128...
Page 90: Uart
UART interrupt. The main elements of the UART and their interactions are shown in the following block diagram. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 90 of 128...
Page 91: Baud Rate Generation
BR: Baud Rate GBRD: Generated baud rate divider UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 91 of 128...
Page 92 19.2 0.04 -0.02 28.8 -0.08 0.01 38.4 -0.08 0.04 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 92 of 128...
Page 93: Data Format
19.3 shows the timing for a UART transaction with parity enabled (PEN = 1). UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 94: Hardware Flow Control
If nCTS goes high while UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 95: Interrupt
UART_BAUD and UART_CR ) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 95 of 128...
Page 96 UART_BAUD Config ure UART_CR Another data is transferred? TX_STRT_INTR=1? UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 96 of 128...
Page 97 5. If another data is to be received ,then go to step 1;else set RX_EN in UART_CR 0 and finish UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 97 of 128...
Page 98 Another data is received? Set rx_en to low in UART_CR UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 98 of 128...
Page 99: Register Description
Table 74 CR Type Reset Symbol Description 31-23 RSVD Reserved UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 99 of 128...
Page 100 1 = parity checking and generation is enabled. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 100 of 128...
Page 101 0 state for a duration longer than one frame transmission time. PE_INT Parity error interrupt status. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 101 of 128...
Page 102 1: Rx buffer is full. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 102 of 128...
Page 103: Watch-Dog Timer (Wdt)
R/W register that enables the software to control the UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 103 of 128...
Page 104: Register Description
FFFFFFFFh VALUE The current value of the decrementing counter. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 104 of 128...
Page 105 WDOGLOAD. Table 81 Watchdog Raw Interrupt Status Register (WDOGRISR) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 105 of 128...
Page 106 0 = Write access to all other registers is enabled.. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 106 of 128...
Page 107 Value output on WDOGRES when in Integration Test Mode UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 107 of 128...
Page 108: Gpio
The figure following shows a block diagram of a single GPIO pin. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 109: External Interrupt/Wakeup Lines
GPIO. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 109 of 128...
Page 110: Tool For Configure Gpio
GPIO pins in a quick and convenient way. The following figure shows the UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual...
Page 111 GUI of QnDriverTools. For more details of QnDriverTools in the SDK, please refer to guide (proper name to be added) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 111 of 128...
Page 112: Register Description
Please see GPIO MUX Table; 14.4.1.2 PIN_MUX_CTRL1 PIN_MUX_CTRL1 Offset = 24h (PMU) UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 112 of 128...
Page 113: Pin_Mux_Ctrl2
0 = CLKOUT0 is HCLK; 1 = CLKOUT0 is CLK_32K UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 113 of 128...
Page 114: Pad_Drv_Ctrl
Every bit control one GPIO PAD driver ability; 0 = Low driver ; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 114 of 128...
Page 115: Pad_Pull_Ctrl0
01b = Pull-down, 10b = Pull-up, 11b = Reserved; UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 115 of 128...
Page 116: Pad_Pull_Ctrl1
14.4.1.7 IO_WAKEUP_CTRL IO_WAKEUP_CTRL Offset = 3Ch (PMU) Description of Word UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 116 of 128...
Page 117: Gpio Register Description
Write 1 Set the interrupt type bit. 0 No effect. UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 117 of 128...
Page 118 Register Description UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 118 of 128...
Page 119 Interrupt type set Table 94 INTTYPECLR Type Reset Symbol Description UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 119 of 128...
Page 120 Description 31-0 INTSTATUS[31-0] Write one to clear interrupt request UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev 1.3 — 05 November 2018 User Manual 120 of 128...
Page 121: Legal Information
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to special or consequential damages (including - without limitation - lost profits, lost...
Page 122: List Of Figures
Figure 12 Watchdog Operation Flow Diagram ....103 Figure 13 Single GPIO pin diagram ........ 109 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev. 1.3 — 05 November 2018 User Manual 122 of 128...
Page 123: List Of Tables
Table 41 Register Map ............67 Table 42 CR ..............67 Table 43 PSCL ..............68 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev. 1.3 — 05 November 2018 User Manual 123 of 128...
Page 124 Table 89 OUTENABLESET..........119 Table 90 OUTENABLECLR ..........119 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev. 1.3 — 05 November 2018 User Manual 124 of 128...
Page 125 Table 96 INTPOLCLR ............. 120 Table 97 INTSTATUS ............. 120 UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Rev. 1.3 — 05 November 2018 User Manual 125 of 128...
Page 126: Table Of Contents
Comparator Inputs ..........46 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, visit: http://www.nxp.com Date of release: 05 November 2018...
Page 127 11.3.2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, visit: http://www.nxp.com Date of release: 05 November 2018...
Page 128 Contents ............. 126 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, visit: http://www.nxp.com Date of release: 05 November 2018...

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Qn9022 Qn9021

NXP Semiconductors QN902 Series User Manual

1 Introduction

2 MCU Subsystem

3 Power Supply and Power Management Unit (PMU)

4 Analog-To-Digital Converter (ADC)

5 Comparator

6 Clock Management Unit (CMU)

7 Inter-Integrated Circuit (I2C) Interface

8 Pwm

9 Real Time Clock (RTC)

10 Serial Peripheral Interface (SPI0/SPI1)

11 Timers

12 Uart

13 Watch-Dog Timer (WDT)

14 Gpio

15 Legal Information

16 List of Figures

17 List of Tables

18 Contents

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