Power And Control Inputs; Control Basics; Power Input; Connectors - Planar EL640.480-A User Manual

Power and Control Inputs

Table 2. Power and Control Inputs

Pin
J2 (Power input connector)
1
2
3
4
J3 (Luminance control input)
1
2

Control Basics

The EL panel is a matrix structure, with column and row electrodes arranged in
X-Y formation. Light is emitted when an AC voltage of sufficient amplitude is
applied at a row-column intersection. The display operation is based on the
symmetric, line at a time data addressing scheme. Input thresholds to the
display are 74ACT CMOS compatible (TTL thresholds).

Power Input

The only required supply voltage for the display is +12Vdc (Vcc2). All internal
high voltages are generated from Vcc2.

Connectors

Table 3. Connectors.

J1
J2
J3
6 EL640.480-A SB Series Operations Manual (020-0358-00A)
Signal Symbol
Voltage Vcc2
Ground GND
Ground GND
Reserved
Luminance LUMPOT1
control
Luminance LUMPOT2
control
34-pin header
Mating
Locking clip
4-pin header
Mating
Protector
2-pin header
Mating
Protector
Description
Supply voltage (+12 Vdc) converted to required internal
voltages
Power return
Power return (same as pin 2)
Reserved for compatibility with Vcc1 input in other Planar
displays. Do not use.
The inputs for an external 50 kΩ  l og potentiometer to
adjust the luminance of the display. If left disconnected,
the luminance is at the max level. See page 9 for details.
ODU 511.266.003.034 or eq.
ODU 517.065.003.034 or eq.
ODU 511.065.734.700 or eq.
Hirose DF1–4P–2.5 DS or eq.
Hirose DF1–4S–2.5 R 24
Hirose DF1–4A 1.33
Hirose DF1–2P–2.5 DS or eq.
Hirose DF1–2S–2.5 R 24
Hirose DF1–2A 1.33