Cs49844A (Digital: U1073); W9864G6Kh-5 (Digital: U1023); Pin Description - Denon AVR-X2400H Service Manual

CS49844A (DIGITAL : U1073)
SD_A3, EXT_A3, 1
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
SD_A10, EXT_A12 5
SD_BA0, EXT_A13
SD_BA1, EXT_A14
SD_CS, EXT_OE
SD_RAS, EXT_CS1 9
SD_CAS, EXT_CS2 10
TEST_EN
VDD1
GND1 13
EE_CS1. GPIO0
EE_CS0, GPIO1 15
DAI1_D5, GPIO69
DAI1_D4, GPIO68 144-Pin LQFP
BDI* DAI1_D3, GPIO67 18
BDI*, DAI1_D2, GPIO66
VDD2
(with Thermal Pad )
GND2 21
BDI*, DAI1_D1, GPIO65
BDI*, DAI1_D0, GPIO64
24
GND3
25
VDD3
BDI*, DAI1_SCLK1, GPIO71
27
BDI*, DAI1_LRCK1, GPIO70
DAI1_LRCK2, GPIO72
DAI1_SCLK2, GPIO73
VDDIO1 30
GNDIO1
RESET
DBDA0 33
DBDA1
DBCK0
35
DBCK1 36
108 DAO3_D3, XMTA, GPIO113
SD_D11, EXT_D3
SD_D12, EXT_D4
105 SD_D13, EXT_D5
GNDIO4
VDDIO4
SD_D14, EXT_D6
101 SD_D15, EXT_D7
100 SD_D0, EXT_D8
SD_D1, EXT_D9
98 SD_D2, EXT_D10
SD_D3, EXT_D11
SD_D4, EXT_D12
95 SD_D5, EXT_D13
94 GND10
CS49844A
VDD10
SD_D6, EXT_D14
91 SD_D7, EXT_D15
Package
90 SD_DQM0, EXT_A15
SD_WE, EXT_WE
DAO3_D6, GPIO35
DA03_D5, GPIO34
86 DAO3_D2, GPIO33
85 DA03_D1, GPIO32
SCP_BSY, GPIO143_OD
83 VDD9
GND9
SCP1_IRQ, GPIO144_OD
80
SCP1_CLK, GPIO148
SCP1_MISO_SDA, GPIO146
GND8
VDD8
76 SCP_MOSI, GPIO147
75 SCP1_CS, GPIO145
SCP2_CS
73 DAO3_D7, XMTB, GPIO115
W9864G6KH-5 (DIGITAL : U1023)

Pin description

5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
23 ~ 26, 22,
A0 A11 Address
29 ~35
20, 21 BS0, BS1 Bank Select
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
DQ0 DQ15
45, 47, 48, 50,
Input/ Output
51, 53
19 Chip Select
CS
Row Address
18
17
CAS Address Strobe Referred to
16 Write Enable
WE
UDQM
Input/output
39, 15
LDQM
38 CLK Clock Inputs
37 CKE Clock Enable
1, 14, 27 V
DD
28, 41, 54 V
SS
Power for I/O
3, 9, 43, 49 V
DDQ
Ground for I/O
6, 12, 46, 52 V
SSQ
36, 40 NC No Connection No connection.
59
W9864G6KH
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A11. Column address: A0 A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Data
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock , CAS and WE define the
Strobe
operation to be executed.
Column
Referred to
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
mask cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
Ground
DRAM.
Separated power from V , to improve DQ noise
DD
buffer immunity.
Separated ground from V , to improve DQ noise
SS
buffer immunity.
Publication Release Date: Nov. 12, 2013
- 5 - Revision A02