Related Manuals for Sys Tec Electronic ECUcore-9G20
Summary of Contents for Sys Tec Electronic ECUcore-9G20
- Page 1 Development Board ECUcore-9G20 Hardware Manual Edition March 2010 System House for Distributed Automation...
- Page 2 Development Board ECUcore-9G20 Status / Changes Status: released Date/ Version Section Change Editor L-1256e_01 initial version K.Becker © SYS TEC electronic GmbH 2010 L-1256e_01...
- Page 3 SYS TEC electronic GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. SYS TEC electronic GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages, which might result.
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Page 5: Table Of Contents
4.5 Ethernet ..................18 4.6 USB .................... 18 4.6.1 USB host ............... 18 4.6.2 USB device..............18 4.7 SD Card ..................19 4.8 EEPROM..................19 4.9 ADC.................... 19 4.10 CAN.................... 20 4.11 RS232 ..................20 © SYS TEC electronic GmbH 2010 L-1256e_01... - Page 6 Figure 2: Block Diagram Developmentboard ECUcore-9G20....5 Figure 3: Positions of components ............6 Figure 4: Default Jumper configuration ............ 7 Figure 5: Jumper pincount................. 7 Figure 6: Pinout (top view) ..............10 © SYS TEC electronic GmbH 2010 L-1256e_01...
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Page 7: Introduction
Introduction 1 Introduction The ECUcore-9G20 Development Board provides a flexible development platform, enabling quick and easy start-up and subsequent programming of the Single Board Computer module. The design of the Development Board allows easy operation of the installed ECUcore in Communication Networks (LAN, USB, CAN) and simple GPIO-Tests by keys and leds. -
Page 9: Ordering Information And Support
2 Ordering Information and Support Order Number Version 4002008 Development Board ECUcore-9G20 Development Board features: • Socket for ECUcore-9G20 (order number: 4001016) • External power supply from 9-36VDC/24W • Switching regulator 9-36VDC / 5VDC • Switching regulator 9-36VDC / 3,3VDC •... -
Page 10: Properties Of The Development Board
Development Board ECUcore-9G20 3 Properties of the Development Board 3.1 Overview The ECUcore-9G20 belongs to SYS TEC’s ECUcore family. The ECUcore-9G20 integrates all elements of a microcontroller system on one board. The module only needs an external power supply (3,3V) to operate. -
Page 11: Block Diagram
Reset-LED Reset Reset-Button USB-Device 1 x USB-Device BOOT BOOT -Button USB-Host 2 x USB-Host 5,0V 3,3V Power Supply Battery 3V3DC 9-36V 9-36V 9-36VDC 9-36VDC jack screw Figure 2: Block Diagram Development Board ECUcore-9G20 L-1256e_01 © SYS TEC electronic GmbH 2010... -
Page 12: Positions Of Elements
Development Board ECUcore-9G20 3.3 Positions of Elements Figure 3: Positions of components © SYS TEC electronic GmbH 2010 L-1256e_01... -
Page 13: Figure 4: Default Jumper Configuration
Properties of the Development Board 3.4 Jumper JP405 Figure 4: Default Jumper configuration Figure 5: Jumper pincount L-1256e_01 © SYS TEC electronic GmbH 2010... - Page 14 Button S403 is on FPGA_IO_76 FPGA_IO_77 JP401 1-2 default LED D405 is on FPGA_IO_77 FPGA_IO_78 FPGA_IO_79 FPGA_IO_80 3-4 default LED D406 is on FPGA_IO_78 FPGA_IO_81 5-6 default Switch Status MRES is on FPGA_IO_79 © SYS TEC electronic GmbH 2010 L-1256e_01...
- Page 15 J400 PCB-Version Bit2 of Version on EBI D10 Bit3 of Version on EBI D11 Write Protect of EEPROM is active EEPROM Write J401 Protect 2-3 default Write Protect of EEPROM is not active L-1256e_01 © SYS TEC electronic GmbH 2010...
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Page 16: Board Connectors
See figure 3 for the position of board connetor X100 and its connector rows. The Development Board ECUcore-9G20 has two board connectors. Each of the SMT male header consists of 100 contacts divided into double rows. In total, the board has 200 contacts. For better emc- properties, 20% of pins are GND. -
Page 17: Usb
USB_HDMB USB_DDM I2C_DATA CAN_TXD I2C_CLK CAN_RXD FPGA_IO0 CAN_VCC FPGA_IO1 FPGA_IO2 FPGA_IO44 FPGA_IO3 FPGA_IO4 FPGA_IO46 FPGA_IO45 FPGA_IO5 FPGA_IO6 FPGA_IO48 FPGA_IO47 FPGA_IO7 FPGA_IO50 FPGA_IO49 FPGA_IO8 FPGA_IO52 FPGA_IO51 FPGA_IO9 FPGA_IO10 Table 1: Pinout high density connectors L-1256e_01 © SYS TEC electronic GmbH 2010... -
Page 18: Table 2: Pinout Expansion Connectors X200
FPGA_IO55 FPGA_IO58 FPGA_IO57 FPGA_IO60 FPGA_IO59 FPGA_IO62 FPGA_IO61 FPGA_IO63 FPGA_IO64 FPGA_IO66 FPGA_IO65 FPGA_IO68 FPGA_IO67 FPGA_IO70 FPGA_IO69 FPGA_IO72 FPGA_IO71 FPGA_IO73 FPGA_IO74 FPGA_IO76 FPGA_IO75 FPGA_IO78 FPGA_IO77 FPGA_IO80 FPGA_IO79 VBAT FPGA_IO81 Table 2: Pinout expansion connectors X200 © SYS TEC electronic GmbH 2010 L-1256e_01... -
Page 19: Table 3: Pinout Expansion Connectors X201
FPGA_IO16 FPGA_IO18 FPGA_IO19 FPGA_IO20 FPGA_IO21 FPGA_IO22 FPGA_IO23 FPGA_IO24 FPGA_IO25 FPGA_IO26 FPGA_IO27 FPGA_IO28 FPGA_IO29 FPGA_IO30 FPGA_IO31 FPGA_IO32 FPGA_IO33 FPGA_IO34 FPGA_IO35 FPGA_IO36 FPGA_IO37 FPGA_IO38 FPGA_IO39 FPGA_IO40 FPGA_IO41 FPGA_IO42 FPGA_IO43 Table 3: Pinout expansion connectors X201 L-1256e_01 © SYS TEC electronic GmbH 2010... -
Page 20: Component Descriptions
This is shown on the silkscreen on the PCB next to the terminal block. From this voltage two switching regulators produce the onboard voltages (5VDC and 3,3VDC). 5VDC are only used for USB host. 3,3VDC supplies the ECUcore and all other peripheral elements. © SYS TEC electronic GmbH 2010 L-1256e_01... -
Page 21: Ice Interface
ICE/JTAG connector X403 If jumper JP503 is closed, signal /JTAGSEL on the ECUcore is set to high level and the Boundary Scan mode on the ECUcore-9G20 is active. Otherwise, if jumper JP503 is open, programming and debugging in ICE-mode is possible. -
Page 22: Table 5: Jtag Connector X502
5-6 closed JTAG-Signal FPGA_TDO is present on Pin 5 of X502 FPGA_TDI 7-8 open JTAG-Signal ARM_TDO is present on Pin 7 of X502 Signal Signal not connected not connected Table 5: JTAG connector X502 © SYS TEC electronic GmbH 2010 L-1256e_01... -
Page 23: I/O Elements
J400 PCB-Version 3,3V FPGA_IO16, FPGA_IO17, FPGA_IO18, FPGA_IO19, FPGA_IO0, FPGA_IO7 Table 6: IO elements connected to the ECUcore connect to Function D604 (yellow) 3,3V 3,3V-Supply D605 (yellow) 5V-Supply Table 7: LEDs connected to onboard ICs L-1256e_01 © SYS TEC electronic GmbH 2010... -
Page 24: Usb Host
The 9G20-CPU has build in an USB device interface. It serves one USB-B connector (X310). There is no power supply on pin 1 of the connector, so the Device interface cannot be detected by the Development Board. © SYS TEC electronic GmbH 2010 L-1256e_01... -
Page 25: Sd Card
Some analog values can be adjusted by Potentiometer R429 and interpreted by software. ECUcore-Pin close jumper JP405 pin 7-8 close jumper JP405 pin 5-6 close jumper JP405 pin 3-4 Table 11: ADC connection L-1256e_01 © SYS TEC electronic GmbH 2010... -
Page 26: Can Connector Pinout
TXD0, RXD0 X300 JP300 5-6, JP301 5-6 TXD1, RXD1 X300 JP300 7-8, JP301 7-8 DTXD, DRXD X301 JP300 3-4, JP301 3-4 TXD2, RXD2 X302 JP300 1-2, JP301 1-2 Table 14: RS232 jumper settings © SYS TEC electronic GmbH 2010 L-1256e_01... - Page 27 Component Descriptions L-1256e_01 © SYS TEC electronic GmbH 2010...
- Page 28 How would you improve this manual? page Did you find any mistakes in this manual? Submitted by: Customer number: Name: Company: Address: Return to: SYS TEC electronic GmbH Published by Ord. No. L-1256e_01 © SYS TEC electronic GmbH 2010 Printed in Germany...
- Page 29 Component Descriptions August-Bebel-Str. 29 D-07973 Greiz GERMANY Fax : +49 (0) 36 61 / 62 79 99...
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