NAD VISO FIVE Service Manual page 47

Pin Layout
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
No. Pin Name
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 SMUTE
CSN
7 ACKS
CCLK
8 DIF0
CDTI
9 P/S
10 AOUTR
11 AOUTL
12 VCOM
13 VSS
14 VDD
15 DZFR
16 DZFL
Note: All input pins except pull-up pin should not be left floating.
MCLK
1
BICK
2
SDTI
3
LRCK 4
PDN 5
6
7
8
PIN/FUNCTION
I/O Function
I Master Clock Input Pin
An external TTL clock should be input on this pin.
I Audio Serial Data Clock Pin
I Audio Serial Data Input Pin
I L/R Clock Pin
I Power-Down Mode Pin
When at "L", the AK4384 is in the power-down mode and is held in reset. The
AK4384 should always be reset upon power-up.
I Soft Mute Pin in parallel mode
"H": Enable, "L": Disable
I Chip Select Pin in serial mode
I Auto Setting Mode Pin in parallel mode
"L": Manual Setting Mode, "H": Auto Setting Mode
I Control Data Clock Pin in serial mode
I Audio Data Interface Format Pin in parallel mode
I Control Data Input Pin in serial mode
I
Parallel/Serial Select Pin
"L": Serial control mode, "H": Parallel control mode
O Rch Analog Output Pin
O Lch Analog Output Pin
O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
- Ground Pin
- Power Supply Pin
O Rch Data Zero Input Detect Pin
O Lch Data Zero Input Detect Pin
16
15
14
13
Top
View
12
11
10
9
2-35
DZFL
DZFR
VDD
VSS
VCOM
AOUTL
AOUTR
P/S
(Internal pull-up pin)