Clock Generator - Hitachi M300N Service Manual

Schematic Diagrams

Clock Generator

+3VS
Sheet 9 of 29
Clock Generator
[4,28] VCCVIDGD
B - 10 Clock Generator (71-M3000-D04)
[3,4,5,6,7,8,11,12,13,14,16,17,18,19,21,23,26,27,28]
FREQUENCY SETUP TABLE
(FS2) (FS1) (FS0) CPU 3V66 66MHz OUT PCI
(MHz) (MHz) (MHz) (MHz)
0 0 0 66.66 66.66 66.66 33.33
0 0 1 100 66.66 66.66 33.33
0 1 0 200 66.66 66.66 33.33
0 1 1 133 66.66 66.66 33.33
1 0 0 66.66 66.66 66MHz_IN 66MHz_IN/2
1 0 1 100 66.66 66MHz_IN 66MHz_IN/2
1 1 0 200 66.66 66MHz_IN 66MHz_IN/2
1 1 1 133 66.66 66MHz_IN 66MHz_IN/2
Mid 0 0
Mid 0 1
Mid 1 0
Mid 1 1
L49
+3VS
HCB2012K-121T30
CT9 C54
+3VS
POSCAP
10u/10V 0.1u_X7R
L48
HCB3216K-800T30
C327
+ C58 C52 C48 C31 C32 C50 C47 C51 C49 C53
47uF/6.3V_D 4.7uF 0.1u_X7R 0.1u_X7R 0.1u_X7R 0.1u_X7R 0.1u_X7R 1000PF 1000PF 1000PF 1000PF
VREG FEATURE
R354
Z1006
+3VS
10K
R340
+3VS
R339
Q1 R362
R353 R350
Z1007 G 2N7002 R363
[13,21] SUSA#
*0
R351
220 [13] PCI_STP#
R352
[13] PM_STPCPU#
[8,12,14] SMB_ICHCLK
[8,12,14] SMB_ICHDATA
R341
+3VS
[4] SEL0
CONNECT TO PIN 41 GND
R337 R51
1K 10K
L37
1 2 VDDCPU
+3VS
HCB2012K-121T30
C26 C294
10u/10V 0.1uF
L2
1 2 VDD48
+3VS
HCB2012K-121T30 F0
C27 C30
10u/10V 0.1uF C325 10p
F2
C324 10p
C55
0.1u_X7R
U4
Z1001 Z1011
26 52 R321 33
VDDA CPUCLKT0
VDD48 37 51 Z1012 R48 33
VDD48 CPUCLKC0
Z1002 1 49 Z1013 R320 33
VDDREF CPUCLKT1
Z1014
48 R49 33
CPUCLKC1
8
VDDPCI
Z1015
14 45 R319 33
VDDPCI CPUCLKT2
44 Z1016 R50 33
CPUCLKC2
19
VDD3V66
32 10 Z1017
VDD3V66 PCICLK0
11 Z1018
PCICLK1
VDDCPU 46 12 Z1019
VDDCPU PCICLK2
50 13 Z1020
VDDCPU PCICLK3
16 Z1021
PCICLK4
17 Z1022
PCICLK5 T
Z1023
28 18
VTT_PWRGD# PCICLK6 T
1K 5 F0 R372 33
PCICLK_F0 CLK_ICHPCI [12]
1K 6 TZ1001
PCICLK_F1
1K 7 F2 R371 *33
INT_APICCLK [12]
PCICLK_F2
*0 Z1003 25
PD#
Z1004
*0 34
PCI_STOP#
*0 Z1005 53 43 Z1024 R336 10K
CPU_STOP# MULTSEL0/REF0
Z1025
56
REF
SMB_ICHCLK 30
SCLK
Z1026
SMB_ICHDATA 29 39
SDATA 48MHz_USB
38 Z1027
48MHz_DOT
2.7K Z1008 54
FS0
55 C313
FS1
Z1009 40 24 Z1028
FS2 3V66_5/66MHz_IN T
33P
33 Z1029
3V66_0 T
Z1010 Z1030
42 35
IREF VCH_CLK/3V66_1
Iref=2.32mA
Z1031
4 21
GND 3V66_2/66MHz_OUT0
9 22 Z1032
GND 3V66_3/66MHz_OUT1
Z1033
15 23
R355
GND 3V66_4/66MHz_OUT2 T
20
GND
475_1% 27
GND
31 2 Z1034 C318
GND X1
36
GND
41 10P
R361
GND
Z1035
47 3
GND X2
1M
ICS950810/TSSOP
Y1
2 1
14.318MHZ
C312 C334
33P 33P
IF CL=18PF DEL C35,36
+3VS
DREFSSCLK_D
R45 R302 R44 R303 R43 R304
49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1%
CLK_CPU_BCLK [4]
CLK_CPU_BCLK# [4]
CLK_ITP_CPU [4]
CLK_ITP_CPU# [4]
CLK_MCH_BCLK [6]
CLK_MCH_BCLK# [6]
R370 33
R369 33
R368 33
R367 33
R366 33
C323 C322 C321 C320 C319
10P 10P 10P 10P 10P
+3VS
R356 33
CLK_ICH14 [13]
R318 33
CLK_ICH48 [13]
R317 33
DREFCLK [5]
C296 C295
10P *10P
R365 33
CLK_ICH66 [12]
R364 33
CLK_MCH66 [5]
C317
10P
R305 33
DREFSSCLK [5]
C288 DREFSSCLK_D R300 *10
10P
C298 C297
1uF 1uF
U25
1 8
CLKIN PD# SUSA# [13,21]
2 7 SSC_SCLK *0 R41
VDD SCLK LCLKCTLA [5]
R52
SMB_ICHCLK [8,12,14]
3 6 SSC_SDATA 0
GND SDATA LCLKCTLB [5,6]
*0 R42
SMB_ICHDATA [8,12,14]
4 5 TZ1002 R53 0
CLKOUT REF_OUT
*ICS91718
PCLK_LAN [18]
PCLKPCM [24]
PCLK_IO [19]
PCLK_H8 [21]
PCLK1394 [20]