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The access motion is initiated at the logical zero to
logical one transition or the trailing edge of this
signal pulse.
Any
change in the DIRECTION IN line
must be made at least lOOns before the leading edge
of the step pulse.
The R/W head will move at the rate of the incoming
step pulses.
The minimum time between successive
steps is
3.0rnS.
The minimum pulse width is
10.0
psec.
See Figure
8
for step timing.
Step pulses issued at 3.QmS intervals results in a
random average access time of l7QmS.
An option
available on the printed circuit board allows
a
decrease in this time.
See Section
4.5.3.
A 220/330
resistor pack allows for line termination.
FIGURE 8
STEP MODE TIMING
lOOnS
MIN.
~I~
I
DIRECTION
CHANG~
-DIRECTION
-STEP
-SEEK COMPLETE
~~~~Z~~~~I----------~-t
S
~
t
3.0
mS
MIN.
"I
~
10.0
uS
MIN.
------:t-t
U
500
uS MAX
_ -.....
~
S~---'-I
__ _
U
:
L
.1Sms
~
----~iiII!I
~
SOOnS TYP.
.-- TYP.
r
*
Change in direction can not be made prior to
seek complete.
18
HEAD
SETTLE
DELAY
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