SEA 222 Operator's Manual page 54

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.2
5.5.3
5.5.4
5.5.5
THE REFERENCE CLOCK OSCILLATOR
The master clock oscillator operates at a frequency of 6400.0 KHz.
This frequency allows the use of a compact, high stability crystal
which is enclosed in a temperature stabilized holder. The combination
of a high stability crystal, capacitors of the proper .temperature
coefficient and crystal temperature stabilization provides excellent
frequency stability over the en vi ronmenta 1 temperature range of the
equipment. Warm up time for the clock oscillator is less than 3
minutes.
The oscillator used is the osc:illator portion of synthesizer chip
Ull. This circuit has been especially designed for use as a stable high
frequency crystal oscillator and also provides the high speed loop
reference divider in the form of the bui 1 t in di vi de-by-R counter.
This counter is set to 1000 and provides the phase detector with a
stable reference of 6.4 KHz.
LOW SPEED LOOP REFERENCE
In order to provide a 100 Hz reference for the low speed (100 Hz)
phase locked loop, a sample of the 6400.0 KHz master clock signal is
divided by 125 in three cascaded quinary counters. Two high speed
quinary counters are provided by U18 and the third by Ul4. The output
from U14 is at a frequency of 51.2 KHz. This 51.2 KHz signal is then
applied to the reference divider input of synthesizer chip Ul6. The
internal divide-by-R counter in U 16 is set to 512 during fire up
initialization, thus providing U16s phase detector with a stable
reference of 100 Hz.
CPU CLOCK DIVIDER
The CPU clock signal for the control computer is also derived from
the master clock oscillator through one of the flip-flops in U18.
Dividing the 6400.0 KHz master clock signal by two provides the CPU
with a stable clock signal at 3200.0 KHz. This is within the allowed
clock range of the CPU and assures that CPU operation wi 11 be sync-
ronous with all other counters in the radio, thus minimizing counter
generated noise and spurious signals.
THE HIGH FREQUENCY DIVIDE-BY-N COUNTER
The high speed di vi de-by-N function is performed through use of the
built in divide-by-N counter in synthesizer chi-p Ull in conjunction
with the dual modulus prescaler chip, U12.
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