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VXI Technology VM1548C User Manual

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VM1548C
TTL I/O M
ODULE
U
'
M
SER
S
ANUAL
P/N: 82-0045-000
Released July 31, 2007
VXI Technology, Inc.
2031 Main Street
Irvine, CA 92614-6509
(949) 955-1894
bus

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  • Page 1 VM1548C TTL I/O M ODULE ’ ANUAL P/N: 82-0045-000 Released July 31, 2007 VXI Technology, Inc. 2031 Main Street Irvine, CA 92614-6509 (949) 955-1894...

  • Page 3: Table Of Contents

    Write/Read Mode ...............................33 ..........................37 EGISTER CCESS XAMPLES ...........................39 XAMPLES & PLUG PLAY 4..................................45 ECTION ............................45 OMMAND ICTIONARY Introduction ................................45 Alphabetical Command Listing ..........................45 Terminology ...............................46 Command Dictionary............................50 IEEE 488.2 C .........................51 OMMON OMMANDS *CLS...................................51 *ESE ...................................52 *ESR? .................................53 *IDN? .................................54 VM1548C Preface...
  • Page 4 VXI Technology, Inc. *OPC ..................................55 *RST...................................56 *STB? .................................57 *TRG ..................................58 *TST ...................................59 *WAI ..................................60 SCPI C .......................61 NSTRUMENT PECIFIC OMMANDS FORMat................................61 INPut:REGister:POLarity...........................62 INPut:REGister:SOURce ...........................63 INPut:TTLTrig ..............................64 INPut:TTLTrig:STATE............................65 OUTPut:CLOCk:ENABle ..........................66 OUTPut:CLOCk:POLarity ..........................67 OUTPut:CLOCk:SOURce..........................68 OUTPut:REGister:POLarity..........................69 OUTPut:REGister:SOURce ..........................70 OUTPut:TTLTrig ...............................71 OUTPut:TTLTrig:POLarity ..........................72 OUTPut:TTLTrig:SOURce ..........................73 OUTPut:TTLTrig:STATE..........................74...
  • Page 5 Clock Enable ..............................102 Latch Data ................................103 Read Data .................................104 ..................................105 NDEX VM1548C Preface...

  • Page 6: Certification

    VXI Technology, Inc. shall not be liable for injury to property other than the goods themselves. Other than the limited warranty stated above, VXI Technology, Inc. makes no other warranties, express or implied, with respect to the quality of product beyond the description of the goods on the face of the contract.

  • Page 7: Declaration Of Conformity

    RODUCT ONFIGURATIONS VXI Technology, Inc. declares that the aforementioned product conforms to the requirements of the Low Voltage Directive 73/23/EEC and the EMC Directive 89/366/EEC (inclusive 93/68/EEC) and carries the “CE” mark accordingly. The product has been designed and manufactured...

  • Page 8: Terms And Symbols

    VXI Technology, Inc. ENERAL AFETY NSTRUCTIONS Review the following safety precautions to avoid bodily injury and/or damage to the product. These precautions must be observed during all phases of operation or service of this product. Failure to comply with these precautions, or with specific warnings elsewhere in this manual, violates safety standards of design, manufacture, and intended use of the product.
  • Page 9 The operator of this instrument is advised that if the equipment is Improper Use used in a manner not specified in this manual, the protection provided by the equipment may be impaired. Conformity is checked by inspection. VM1548C Preface...
  • Page 10 VXI Technology, Inc. UPPORT ESOURCES Support resources for this product are available on the Internet and at VXI Technology customer support centers. VXI Technology World Headquarters VXI Technology, Inc. 2031 Main Street Irvine, CA 92614-6509 Phone: (949) 955-1894 Fax: (949) 955-3041...

  • Page 11: Section 1

    J202 as well. In addition to these three standard configurations, the VM1548C may be combined with any of the other members of the VMIP family to form a customized and highly integrated instrument (see Figure 1-1). This allows the user to reduce system size and cost by combining the VM1548C with two other instrument functions in a single wide, C-size VXIbus module.

  • Page 12: Features

    VXI Technology, Inc. Regardless of whether the VM1548C is configured with other VM1548C modules or with other VMIP modules, each group of 48 channels is treated as an independent instrument in the VXIbus chassis and as such, each group has its own FAIL/POWER and ACCESS/ERROR indicators.

  • Page 13: Description

    The RC network consists of a 120 Ω resistor in series with a 100 pF capacitor, giving a time constant of 12 ns. The VM1548C can be combined with any member of the VMIP family to form a customized and highly integrated instrument.
  • Page 14 DATA I/O CLKOUTENA DAMPING WRITE RESISTOR DATA ISENSE READ DATA CLKINENA I/O* OUTENA TTL TIGGER 0-7 CLK OUT SELECT TRIGGER SELECT CLK IN CLOCK SELECT SELECT CLKOUTENA 100pF TTL TRIG OUT SEL 1-3: VM1548C M IGURE ODULE LOCK IAGRAM VM1548C Introduction...

  • Page 15: Vm1548 Specifications

    LOCKED NPUT ETUP ≥ 2 µs LOCKED NPUT ≥ 0 LOCKED UTPUT ≤ 2 µs OWER EQUIREMENTS +5 V @ 864 mA, +12 V @ 60 mA OOLING EQUIREMENTS 0.4 L/s VM1548C-1 0.8 L/s VM1548C-2 1.2 L/s VM1548C-3 VM1548C Introduction...
  • Page 16 VXI Technology, Inc. VM1548C Introduction...

  • Page 17: Section 2

    All components should be immediately inspected for damage upon receipt of the unit. Once the VM1548C is assessed to be in good condition, it may be installed into an appropriate C-size or D-size VXIbus chassis in any slot other than slot 0. The chassis should be checked to ensure that it is capable of providing adequate power and cooling for the VM1548C.

  • Page 18: Setting The Logical Address

    OGICAL DDRESS The logical address of the VM1548C is set by a single 8-position DIP switch located near the module’s backplane connectors (this is the only switch on the module). The switch is labeled with positions 1 through 8 and with an ON position. A switch pushed toward the ON legend will signify a logic 1;...

  • Page 19: Front Panel Interface Wiring

    The 96-channel version (VM1548C-2) will have J201 and J202 provided, while the 144-channel version (VM1548C-3) will have J200, J201 and J202. The wiring for each of these connectors is identical and since each group of 48 channels is treated as a separate instrument, the module will have three Channel 1s, three Channel 2s, three Channel 3s, etc.

  • Page 20: Section 3

    PIN 34 PIN 68 2-2: J200, J201, J202 P IGURE OCATIONS ECTION ROGRAMMING NTRODUCTION The VM1548C is a VXIbus message-based device whose command set is compliant with the Standard Command for Programmable Instruments (SCPI) programming language. VM1548C Preparation for Use...
  • Page 21 The actual commands sent can be in upper case, lower case, or mixed case (case is only used to distinguish short and long form for the user). As an example, these commands are all correct and all have the same effect: TRIGger:SEQuence:IMMediate trigger:sequence:immediate TRIGGER:SEQUENCE:IMMEDIATE TRIG:SEQuence:IMMediate TRIG:SEQ:IMMediate TRIG:SEQ:IMM trig:seq:IMM trig:seq:imm VM1548C Programming...

  • Page 22: Notation

    VXI Technology, Inc. The following command is not correct because it uses part of the long form of TRIGger, but not all the characters of the long form: (incorrect syntax - extra "g"- only trig or trigger is correct) trigg:seq:imm All of the SCPI commands also have a query form unless otherwise noted.

  • Page 23: Examples Of Scpi Commands

    If CLK2 is a logic low level, then the following SCPI command would allow a logic high level on the backplane. TTLTRIG 4 will not pull the line OUTPut:TTLTrig:POLarity INVERT Likewise, continuing with this example, the following command would produce a logic low level on the backplane. TTLTRIG 4 will pull the line low OUTPut:TTLTrig:POLarity NORMal VM1548C Programming...

  • Page 24: Interrupt Circuit

    NTERRUPT IRCUIT This section deals with the interrupt circuit. The VM1548C has the capability to interrupt the slot 0 controller via the VMIP with either a high going edge or with a low going edge of the IRQ* signal. The timing and control circuitry can select one of the six EXTERNAL clocks, GLOBAL (TRIGOUT) or NONE as the interrupt trigger.

  • Page 25: Output Register Circuit

    CLK5 signal is a steady logic low and the clock edge is produced by toggling the clock polarity. SOURce:DATA:ENABle 5 ON OUTPut:REGister:SOURce 5 EXTERNAL OUTPut:REGister:POLarity 5 NORMAL SOURce:DATA 5 205 This provides a rising edge clock OUTPut:REGister:POLarity 5 INVERT VM1548C Programming...

  • Page 26: Input Register Circuit

    VXI Technology, Inc. NPUT EGISTER IRCUIT This section refers to the bi-directional port when configured as an input. The SCPI command used to configure a port as an input is: SOURce:DATA:ENABle <port #> OFF The port is programmable to allow the data to be transparent or clocked. If the port is clocked, there are several choices for the clock source.

  • Page 27: Bi-Directional Clock Circuit

    To drive IMMEDIATE out as CLK5 on the external connector, the following SCPI commands would be issued: OUTPut:CLOCk:ENABle 5 ON OUTPut:CLOCk:SOURce IMMEDIATE To select no clock, the NONE parameter is used. This will always be a logic level low. OUTPut:CLOCk:ENABle 5 ON OUTPut:CLOCk:SOURce NONE VM1548C Programming...

  • Page 28: Application Examples

    The code is functional and will contain a brief description and block diagram of the operation. RITE In this example the VM1548C will be set up prior to receiving the UUT generated clock edge. The VM1548C will output one (1) 16-bit binary word to the UUT from ports 0 and 1. COMMANDS...
  • Page 29 UUT. When these commands are received the VM1548C timing and control circuitry will generate the PORTENA* signal to the port decoder. The port decoder then clocks the write clock enable latch selecting the CLKOUTENA.

  • Page 30: Read Mode

    VM1548C module sends an Interrupt Request (IRQ*) informing the slot 0 controller that the transfer has occurred. In this example the VM1548C will be configured to clock the UUT and read 24 bits of data, when the TTL Trigger line 1 is activated. The TTL Trigger is assumed to be pulled by another instrument used during this test.
  • Page 31 Port TINSEL0,1,2 Address 0,1,2 Decoder Trigger D8-D15 Select CLKIN <port> IN*/OUT <port> Input Data Read <port> Buffers Read / (ports 3,4,5) Read Write Data Bus Data Word Buffer Buffer Data Bus 3-2: R TTL T IGURE SING RIGGER VM1548C Programming...
  • Page 32 When the TTL trigger 1 occurs, the VM1548C will send a high going pulse to clock data out of the UUT. The falling edge of this pulse is used to latch the data into the VM1548C’s I/O data buffers. The VM1548C sends an Interrupt Request (IRQ*) informing the slot 0 controller via the VMIP that the transfer has occurred and that the data in the I/O data buffers is now available.

  • Page 33: Write/Read Mode

    Generates a word serial event to transfer data and TRIG:SEQ:IMM clocks from ports 0, 1, and 2 Read data from port 3 READ? 3 Read data from port 4 READ? 4 Read data from port 5 READ? 5 See Figure 3-3 for the Write/read block diagram. VM1548C Programming...
  • Page 34 UUT. When the commands are received, the VM1548C timing and control circuitry will generate the PORTENA* signal to the port decoder. The port decoder then clocks the write clock enable latch selecting the CLKINENA. The CLKINENA signals are applied to the I/O data and word buffers enabling the input clock line.
  • Page 35 TRIG:SEQ:IMM command will generate a short pulse that will initiate the transfer of data from ports 0, 1, and 2 to ports 3, 4, and 5. When CLK 5 has been received, the VM1548C module sends an Interrupt Request (IRQ*) informing the slot 0 controller via the VMIP that the transfer has occurred.
  • Page 36 VXI Technology, Inc. 3-1: W ABLE ROUND ABLE FROM Signal Signal DATA0.0 DATA3.0 DATA0.1 DATA3.1 DATA0.2 DATA3.2 DATA0.3 DATA3.3 DATA0.4 DATA3.4 DATA0.5 DATA3.5 DATA0.6 DATA3.6 DATA0.7 DATA3.7 I/O*0 I/O*3 CLK0 CLK3 DATA1.0 DATA4.0 DATA1.1 DATA4.1 DATA1.2 DATA4.2 DATA1.3 DATA4.3 DATA1.4 DATA4.4...

  • Page 37: Register Access Examples

    CCESS XAMPLES The VM1548C module supports direct register access for very high-speed data retrieval. The register map is as specified in Table 3-2. As can be seen from the register map in Table 3-2, each 16-bit wide register is shared by two ports.
  • Page 38 VXI Technology, Inc. The Model VM1548C Digital I/O Module supports direct access to the six 8-bit data ports via the Device Dependent Registers of VXIbus interface. The specific registers are located in A16 Memory at offsets 0x20 = Port1, 0x21 = Port0, 0x22 = Port3, 0x23 = Port2, 0x24 = Port5 and 0x25 = Port4.

  • Page 39: Vxi Plug & Play Examples

    TRIGOUT vtvm1548_CLK_SOURCE_NONE Ground ViBoolean polarity - This parameter is used to set the polarity of the clock circuit associated with the specified port. This parameter is considered only if the specified clock source is either vtvm1548_CLK_SOURCE_TTLT or tvm1548_CLK_SOURCE_GLOB. VM1548C Programming...
  • Page 40 VXI Technology, Inc. Valid Values: Interpretation: ------------ -------------- vtvm1548_POL_NORM Normal Polarity vtvm1548_POL_INVERT Inverted Polarity (1) ViInt16 data - This parameter is used to specify the 8 bit data value that is to be written to the output port. Valid Range:...
  • Page 41 Port Five ViInt16 clkSource - This parameter is used to set the source of the clock circuit associated with the specified port. Valid Values: Interpretation: ------------ -------------- vtvm1548_CLK_SOURCE_IMM Word Serial Event vtvm1548_CLK_SOURCE_TTLT VXIbus TRIGIN vtvm1548_CLK_SOURCE_GLOB TRIGOUT vtvm1548_CLK_SOURCE_NONE Ground VM1548C Programming...
  • Page 42 VXI Technology, Inc. ViBoolean polarity - This parameter is used to set the polarity of the clock circuit associated with the specified port. This parameter is considered only if the specified clock source is either vtvm1548_CLK_SOURCE_TTLT or vtvm1548_CLK_SOURCE_GLOB. Valid Values:...
  • Page 43 * Trigger the input port using the IMMEDIATE pulse. status = vtvm1548_triggerSeqImmediate(instrHndl); if (status < VI_SUCCESS) return status; * Read the 8 bit data from a specified input port. status = vtvm1548_readInstrument(instrHndl,portNumber,data); if (status < VI_SUCCESS) return status; return VI_SUCCESS; VM1548C Programming...
  • Page 44 VXI Technology, Inc. VM1548C Programming...

  • Page 45: Section 4

    OMMAND ISTING The following tables provide an alphabetical listing of each command supported by the VM1548C along with a brief description. If an X is found in the column titled *RST, then the value or setting controlled by this command is possibly changed by the execution of the *RST command. If no X is found, then *RST has no effect.

  • Page 46: Terminology

    A query will return a value the specified register was set to. The query Queries syntax is a command followed by a ?, (i.e., INPut:TTLTrig is the set command and INPut:TTLTrig? is the query). Query only commands do not have a set command associated with it, (i.e., READ?.) VM1548C Command Dictionary...
  • Page 47 Set the OPC bit in the Event Status Register. *RST Resets the module to a known state. *STB? Query the Status Byte Register. *TRG Causes a trigger event to occur. *TST? Starts and reports a self-test procedure. *WAI Halts execution and queries. VM1548C Command Dictionary...
  • Page 48 STATus:INTerrupt:ENABle Enables or disables Interrupts to the backplane. NONE STATus:INTerrupt:PTRansition Sets Interrupts to occur on a positive transition. STATus:INTerrupt:NTRansition Sets Interrupts to occur on a negative transition. TRIGger:SEQuence:IMMediate A word serial event which generates a short pulse. VM1548C Command Dictionary...
  • Page 49 Queries the Questionable Status Condition STATus:QUEStionable:CONDition? Register STATus:QUEStionable:ENABle Sets the Questionable Status Enable Register. STATus:PRESet Presets the Status Register. SYSTem:ERRor? Queries the Error Queue Clears queue Queries which version of the SCPI standard the SYSTem:VERSion? module complies with. VM1548C Command Dictionary...

  • Page 50: Command Dictionary

    Describes in detail what the command does and refers to additional sources. Description Present the proper use of each command and its query (when available). Examples Lists commands that affect the use of this command or commands that are affected by Related Commands this command. VM1548C Command Dictionary...

  • Page 51: Ieee 488.2 Common Commands

    *RST Value None Query Syntax Query Parameters Query Response This command clears all event registers, clears the OPC flag and clears all queues Description (except the output queue). Examples Command / Query Response (Description) *CLS None Related Commands VM1548C Command Dictionary...

  • Page 52: Ese

    Bit 0 - Operation Complete Bit 1 - Request Control (not used in the VM1548C) Bit 2 - Query Error Bit 3 - Device Dependent Error (not used in the VM1548C) Bit 4 - Execution Error Bit 5 - Command Error...

  • Page 53: Esr

    Bit 1 - Request Control (not used in the VM1548C, always 0) Bit 2 - Query Error Bit 3 - Device Dependent Error (not used in the VM1548C, always 0) Bit 4 - Execution Error Bit 5 - Command Error...

  • Page 54: Idn

    Query Parameters ASCII character string Query Response The Identification query returns the identification string of the VM1548C module. The Description response is divided into four fields separated by commas. The first field is the manufacturer’s name, the second field is the model number, the third field is an optional serial number and the fourth field is the firmware revision number.

  • Page 55: Opc

    The Operation Complete command sets the OPC bit in the Event Status Register when Description all pending operations have completed. The Operation Complete query will return a 1 to the output queue when all pending operations have completed. Examples Command / Query Response (Description) *OPC *OPC? *WAI Related Commands VM1548C Command Dictionary...

  • Page 56: Rst

    The Reset command resets the module’s hardware and software to a known state. See the Description command index at the beginning of this section for the default parameter values used with this command. Examples Command / Query Response (Description) *RST None Related Commands VM1548C Command Dictionary...

  • Page 57: Stb

    Bit 2 - Error Queue Has Data Bit 4 - Questionable Status Summary (over-current) Bit 5 - Message Available Bit 6 - Master Summary Status Bit 7 - Operation Status Summary Examples Command / Query Response (Description) *STB? None Related Commands VM1548C Command Dictionary...

  • Page 58: Trg

    Command Parameters *RST Value None Query Syntax Query Parameters Query Response This command generates a short pulse or a word serial event for the trigger signal. Description Examples Command / Query Response (Description) *TRG See TRIGger:SEQuence:IMMediate Related Commands VM1548C Command Dictionary...

  • Page 59: Tst

    Command Parameters *RST Value *TST? Query Syntax None Query Parameters Numeric value Query Response The Self-Test query causes the VM1548C to run its self-test procedures and report on the Description results. Examples Command / Query Response (Description) *TST? None Related Commands...

  • Page 60: Wai

    No Operation Pending message is true. This command makes sure that all previous commands have been executed before proceeding. It provides a way of synchronizing the module with its commander. Examples Command / Query Response (Description) *WAI *OPC Related Commands VM1548C Command Dictionary...

  • Page 61: Instrument Specific Scpi Commands

    : Expresses numbers in an 8-digit, leading 0 format. BINary Examples Command / Query Response (Description) FORM:ASC SOUR:DATA 0 58 SOUR:DATA? 0 FORM:HEX #H3A SOUR:DATA? 0 FORM OCT #Q072 SOUR:DATA? 0 FORM BIN #B00111010 FORM:SOUR? 0 SOURce:DATA? <port> Related Commands READ? <port> VM1548C Command Dictionary...

  • Page 62: Input:register:polarity

    Note, that it is important to remember that the input register must be operating in clocked mode in order for the polarity to affect the Input Register latching. Examples Command / Query Response (Description) INP:REG:POL 0 NORM NORM INP:REG:POL? 0 INPut:REGister:SOURce <port #><source> Related Commands VM1548C Command Dictionary...

  • Page 63: Input:register:source

    This selects the Word Serial Event as the clock source. IMMediate See: trigger:sequence:immediate This selects TRIGOUT as the clock source. See: GLOBal OUTPut:TTLTrig:SOURce Examples Command / Query Response (Description) INP:REG:SOUR 0 TTLT TTLT INP:REG:SOUR? 0 INPut:REGister:POLarity <port #><edge> Related Commands VM1548C Command Dictionary...

  • Page 64: Input:ttltrig

    The Input TTLTrig command controls which of the 8 VXI trigger lines will be selected Description as TRIGIN. The 8 VXI trigger lines feed into an 8 to 1 multiplexer. The selected signal is called TRIGIN. Examples Command / Query Response (Description) INP:TTLT 0 INP:TTLT? INPut:TTLTrig:STATe <boolean> Related Commands VM1548C Command Dictionary...

  • Page 65: Input:ttltrig:state

    Query Response The Input TTLTrig state command enables or disables the multiplexer allowing the Description selection of a specific VXI trigger line as TRIGIN. Examples Command / Query Response (Description) INP:TTLT:STAT 0 INP:TTLT:STAT? INPut:TTLTrig <n> Related Commands VM1548C Command Dictionary...

  • Page 66: Output:clock:enable

    0 or OFF - Means the associated port’s external clock line will be an input 1 or ON - Means the associated port’s external clock line will be an output Examples Command / Query Response (Description) OUTP:CLOC:ENAB 0 ON OUTP:CLOC:ENAB? 0 OUTPut:CLOCk:POLarity <port> <edge> Related Commands OUTPut:CLOCk:SOURce <port> <source> VM1548C Command Dictionary...

  • Page 67: Output:clock:polarity

    Note: It is important to remember that the output clock source should be either GLOBAL or one of the eight TTLTrigger lines to control polarity. Examples Command / Query Response (Description) OUTP:CLOC:POL 0 NORM NORM OUTP:CLOC:POL? 0 OUTPut:CLOCk:ENABle <port> <boolean> Related Commands OUTPut:CLOCk:SOURce <port> <source> VM1548C Command Dictionary...

  • Page 68: Output:clock:source

    This selects the Word Serial Event as the clock source. IMMediate: See TRIGger:SEQuence:IMMediate This selects TRIGOUT as the clock source. GLOBal: See OUTPut:TTLTrig:SOURce. Examples Command / Query Response (Description) OUTP:CLOC:SOUR 0 TTLT TTLT OUTP:CLOC:SOUR? 0 OUTPut:CLOCk:ENABle <port> <boolean> Related Commands OUTPut:CLOCk:POLarity <port> <edge> VM1548C Command Dictionary...

  • Page 69: Output:register:polarity

    Note, that it is important to remember that the output register must be operating in clocked mode in order for the polarity to affect the Output Register latching. Examples Command / Query Response (Description) OUTP:REG:POL 0 NORM NORM OUTP:REG:POL? 0 OUTPut:REGister:SOURce <port> <source> Related Commands VM1548C Command Dictionary...

  • Page 70: Output:register:source

    : This selects TRIGOUT as the clock source. GLOBal See: OUTPut:TTLTrig:SOURce. Note: The NONE selection is single buffered; all other selections are double buffered. Examples Command / Query Response (Description) OUTP:REG:SOUR 0 IMM OUTP:REG:SOUR? 0 OUTPut:REGister:POLarity Related Commands INPut:TTLTrigger INPut:TTLTrig:STATe *TRG TRIGger:SEQuence:IMMediate OUTPut:TTLTrig:SOURce VM1548C Command Dictionary...

  • Page 71: Output:ttltrig

    0, 1, 2, 3, 4, 5, Query Response The Output TTLTrig command controls which of the 8 VXI trigger lines will be Description configured as TRIGOUT. Examples Command / Query Response (Description) OUTP:TTLT 0 OUTP:TTLT? OUTPut:TTLTrig:STATE <boolean> Related Commands OUTPut:TTLTrig:SOURce <source> VM1548C Command Dictionary...

  • Page 72: Output:ttltrig:polarity

    Note: It is important to remember that the output TILT Source should be one of the six external clocks. Examples Command / Query Response (Description) OUTP:TTLT:POL NORM NORM OUTP:TTLT:POL? OUTPut:TTLTrig <n> Related Commands OUTPut:TTLTrig:STATe <boolean> OUTPut:TTLTrig:SOURce <source> VM1548C Command Dictionary...

  • Page 73: Output:ttltrig:source

    IMMediate : This selects the Word Serial Trigger event as TRIGOUT. See *TRG and TRIGger:SEQuence:IMMediate. : This parameter routes Ground to TRIGOUT thereby selecting no signal NONE: as TRIGOUT. Examples Command / Query Response (Description) OUTP:TTLT:SOUR IMM OUTP:TTLT:SOUR? INPut:REGister:SOURce Related Commands OUTPut:CLOCk:SOURce OUTPut:REGister:SOURce OUTPut:TTLTrig OUTPut:TTLTrig:STATe OUTPut:TTLTrig:POLarity STATus:INTerrupt:ENABle VM1548C Command Dictionary...

  • Page 74: Output:ttltrig:state

    Query Response The Output TTLTrig State command enables or disables the selected trigger line driven Description by the TTL TRIGGER onto the VXIbus. Examples Command / Query Response (Description) OUTP:TTLT:STAT OFF OUTP:TTLT:STAT? OUTPut:TTLTrig <n> Related Commands OUTPut:TTLTrig:SOURce <source> VM1548C Command Dictionary...

  • Page 75: Read

    (clocked or transparent) can also affect what data is currently in the register. Examples Command / Query Response (Description) The data currently in the register. READ? 2 SOURce:DATA:ENABle <port> <boolean> Related Commands INPut:REGister:SOURce <port> <source> FORMat <type> VM1548C Command Dictionary...

  • Page 76: Read? Clocks

    0 through 5. Examples Command / Query Response (Description) 24 (See table below.) READ? CLOC OUTPut:CLOCk:ENABle Related Commands Bits Clock lines 3 and 4 high would return a decimal value of 24. VM1548C Command Dictionary...

  • Page 77: Read? Control

    User I/O Control Port Output Input (Default condition) Output Output Examples Command / Query Response (Description) 12 (See table below.) READ? CONT SOURce:DATA:ENABle Related Commands Bits I/O Control lines 2 and 3 would return a decimal value of 12. VM1548C Command Dictionary...

  • Page 78: Read? Isense

    DRIVERS Over-Current I/O Lines Sense Lines 8 ea. Port 6 ea. Bit PORT 0 PORT 1 PORT 2 BITS PORT 3 PORT 4 PORT 5 Examples Command / Query Response (Description) READ? ISEN RESet:ISENse Related Commands *STB? VM1548C Command Dictionary...

  • Page 79: Reset:isense

    Each bit corresponds to a group of six lines. It wold be most common just to reset all the lines at once by entering 255. See READ? ISENse for more information. Examples Command / Query Response (Description) RES:ISEN 255 (Resets all the 6-line groups.) READ? ISENse Related Commands *STB? VM1548C Command Dictionary...

  • Page 80: Source:data

    (clocked or transparent) can also affect what data is actually presented to the external connector. Examples Command / Query Response (Description) SOUR:DATA 0 87 SOUR:DATA? 0 SOURce:DATA:ENABle <port> <boolean> Related Commands OUTPut:REGister:SOURce <port> <source> FORMat <type> VM1548C Command Dictionary...

  • Page 81: Source:data:enable

    ON or 1 sets the port as an output, OFF or 0 sets the port as an input. Examples Command / Query Response (Description) SOUR:DATA:ENAB 0 ON SOUR:DATA:ENAB? 0 SOURce:DATA <n> Related Commands READ? <port #> VM1548C Command Dictionary...

  • Page 82: Source:data:polarity

    Query Response The Source Data Polarity command sets the output polarity on an 8-bit port. Description Examples Command / Query Response (Description) SOUR:DATA:POL 1 INV (Inverts the output on port 1.) SOUR:DATA:POL? 1 SOURce:DATA:ENABle <port> <boolean> Related Commands VM1548C Command Dictionary...

  • Page 83: Status:interrupt:enable

    : This selects TRIGOUT as the interrupt trigger. See TTLTRIG diagram. GLOB : This parameter will select GROUND as the interrupt trigger source, NONE thus providing a logic level low Examples Command / Query Response (Description) STAT:INT:ENAB EXT3 EXT3 STAT:INT:ENAB? STATus:INTerrupt:PTRansition <boolean> Related Commands STATus:INTerrupt:NTRansition <boolean> VM1548C Command Dictionary...

  • Page 84: Status:interrupt:ntransition

    GLOBAL or 1 of the 6 external clocks for setting the interrupt trigger source to occur on a negative transition. Examples Command / Query Response (Description) STAT:INT:NTR 1 STAT:INT:NTR? STAT:INT:NTR 0 STAT:INT:NTR? STAT:INT:PTR? STATus:INTerrupt:ENABle <source> Related Commands STATus:INTerrupt:PTRansition <boolean> VM1548C Command Dictionary...

  • Page 85: Status:interrupt:ptransition

    GLOBAL or 1 of 6 external clocks for setting the interrupt trigger source to occur on a positive transition. Examples Command / Query Response (Description) STAT:INT:PTR 1 STAT:INT:PTR? STAT:INT:PTR 0 STAT:INT:PTR? STAT:INT:NTR? STATus:INTerrupt:ENABle <source> Related Commands STATus:INTerrupt:NTRansition <boolean> VM1548C Command Dictionary...

  • Page 86: Trigger:sequence:immediate

    Command Parameters *RST Value None Query Syntax Query Parameters Query Response This command generates a short pulse or a word serial event for the trigger signal. Description Examples Command / Query Response (Description) TRIG:SEQ:IMM *TRG Related Commands VM1548C Command Dictionary...

  • Page 87: Scpi Required Commands

    Query Parameters Query Response The Status Operation Event Register query is included for SCPI compliance. The Description VM1548C does not alter any of the bits in this register and always reports a 0. Examples Command / Query Response (Description) STAT:OPER?

  • Page 88: Status:operation:condition

    Query Parameters Query Response The Operation Status Condition Register query is provided for SCPI compliance only. Description The VM1548C does not alter the state of any of the bits in this register and always reports a 0. Examples Command / Query...

  • Page 89: Status:operation:enable

    Query Response The Operation Status Enable Register is included for SCPI compatibility and the Description VM1548C does not alter any of the bits in this register. The register layout is as follows: Bit 0 - Calibrating Bit 1 - Setting...

  • Page 90: Status:preset

    Command Syntax None. Command Parameters *RST Value None - command only Query Syntax Query Parameters Query Response The Status Preset command enables the over-current questionable event. Description Examples Command / Query Response (Description) STAT:PRES None Related Commands VM1548C Command Dictionary...

  • Page 91: Status:questionable:condition

    Note: This is an internal latched over-current condition. The over-current condition must be removed, and the RESet:ISENse command issued, in order to reset this indication. Examples Command / Query Response (Description) STAT:QURES:COND? None Related Commands VM1548C Command Dictionary...

  • Page 92: Status:questionable:enable

    Register. If this bit is set, an over-current can cause an interrupt. The Status Questionable Enable query reports the contents of the Questionable Status Enable Register. Examples Command / Query Response (Description) STAT:QUES:ENAB 1 STAT:QUES:ENAB? None Related Commands VM1548C Command Dictionary...

  • Page 93: Status:questionable:event

    Query Response 1 = over-current condition The Questionable Status Event Register query indicates if there is an over-current Description condition. Note: Reading the Event Register clears the bit. Examples Command / Query Response (Description) STAT:QUES? None Related Commands VM1548C Command Dictionary...

  • Page 94: System:error

    Volume 2: Command Reference for details on errors and reporting them. Refer to the “Error Messages” section of this manual for specific details regarding the reported errors. Examples Command / Query Response (Description) -350, “Queue overflow” SYST:ERR? None Related Commands VM1548C Command Dictionary...

  • Page 95: System:version

    SYSTem:VERSion? Queries the SCPI version number with which the VM1548C complies. Purpose Required SCPI command Type None - query only Command Syntax Command Parameters *RST Value SYSTem:VERSion? Query Syntax None Query Parameters Numeric ASCII value Query Response The System Version query reports version of the SCPI standard with which the Description VM1548C complies.
  • Page 96 VXI Technology, Inc. VM1548C Command Dictionary...

  • Page 97: Section 5

    4 megabytes per second (MB/s). The VM1548C contains 22 Ω series damping resistors on all data lines to reduce ringing during a data transition period and a RC network of a 120 Ω resistor in series with a 100 pF capacitor for termination of clock lines.

  • Page 98: Vxi Interface

    RANSFERS RITE When write transfers to the UUT are selected, the VM1548C will select the direction of the transfer, enable the clocks for the selected channel(s), latch the data into the I/O word buffer and clock the I/O data buffer using the appropriate triggering method.

  • Page 99: Data Load

    Address 0,1,2 Control D8-D15 IN*/OUT0 CLKOUTENA0 PORT1* Read Data Clock Buffer 100K Read / Enable WRITE0 Write Data Bus Output to Data Front Panel Buffer Word Buffer Data Bus Data Bus 5-1: W IGURE RITE UFFER ONFIGURATION VM1548C Theory Of Operation...

  • Page 100: Device Triggering (Ttl Input Trigger)

    The VM1548C is capable of both receiving and generating VXI TTL triggers. The generated TTL triggers may be used to signal another VXI instrument that a VM1548C event has occurred. The VM1548C can also receive any one of eight TTL triggers from the VXI backplane, TTL trigout, or a front panel connector clock line for use in triggering all six channels at once.
  • Page 101 DOE* Control CLKOUT0 VMIP TINENA* PORT3* Port TINSEL0,1,2 Trigger Decoder Address 0,1,2 CLKOUT0 Select D8-D15 Data Buffer Read / Write Word Data Bus Data Bus Data Bus Data Buffer Buffer 5-2: TTL T IGURE RIGGER NPUT VM1548C Theory Of Operation...

  • Page 102: Device Transfers (Read Mode)

    EVICE RANSFERS When read transfers from the UUT are selected, the VM1548C will select the direction of the transfer, enable the clocks for the selected channel(s), latch the data into the I/O Data Buffer, if double buffering is selected, using the appropriate triggering method and clock the I/O Word Buffer.

  • Page 103: Latch Data

    UFFER ONFIGURATION The CLK0 input from the UUT is terminated in the VM1548C by a RC network of 120 Ω to ground through a 100 pF capacitor and a 47 kΩ resistor to VCC. This termination value gives a time constant of 12 ns for fast rise times on input clocks and will not load the UUT driving source.

  • Page 104: Read Data

    Note that data inputs to the module do not contain pull-up or down-biasing resistors. If the user does not provide active or passive biasing of the data inputs, a read of the port may result in either a “1” or “0” being read from the data inputs. VM1548C Theory Of Operation...

  • Page 105: Index

    ..................21, 22 tree-structured language ..............21 TRIGger:SEQuence:IMMediate ............ 86 TRIGOUT ........25, 26, 27, 46, 63, 68, 70, 71, 83 TTL Trigger..................30 logical address ................17, 18 TTLTRIG ...............23, 27, 46, 63, 83 TTLTRIGGER .................23, 46 message-based ................21 VM1548C Index...
  • Page 106 VXI Technology, Inc. VMIP ............. 11, 12, 30, 97, 98, 102, 104 VXI .......... 11, 30, 32, 38, 97, 98, 100, 103, 104 VXI message-based interface ............13 VXIbus....................21 WEEE ....................8 Write mode ..................28 Write/read mode ................33 VM1548 Index...

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