Hitachi GCR-8480B User Manual page 18

• IC501 (HMS895300) : DSP+ATAPI DECODER+DRAM + µ-COM
Block Diagram
LA9238
Audio
Circuit
ZRESET
HOST
FGCNT CMDI
SW1
SW2
SW3
IOPORT
0~14
*1 EFMIN,EFMIN2,PH,BH,FE,TE,TES,RREC
*2 RHLD,TSH,EQS,GHS,LDON,FBAL,TBAL,TOFST,SGC
*3 LOUT,ROUT,DOUT
*4 DD~DD15,ZDASP,ZPDIAG
*5 ZCSIFX,ZCS3FX,DA0~2,ZDIOR,ZDIOW,ZDMACK,ZHRST,CSEL
*6 DMARQ,HINTRQ,ZIOCS16,IORDY
*7 ZRD,ZWR,ZCS,MCK,SUA0~7
*8 D0~7
*9 CRCERR/FLOCK,HFLO/WRQ/DIR/TLOCK,FSEQ,FSX/LRCK/FV,EFLG/ CK2/PRF,C2F/PCK,EFMOUT
*10 TEST0~2
*11 PCKISTF,PCKIFTP,PDO,POS1~3,RF
*12 SLCO0~3,JITC,DSLB,PHC,BHC
*13 PLL1
*14 SLCIT1~2,AD1,VREF,CSS
16
Driver
TDO, FDO
SLDO, SPDO
FG
*11 VCEC
PLL
*1
*12
CD-DSP
*2
*14
SRAM
*3
FGCNT
CD-DSP I/F
& SYNC
Detector
Merge
CMDI
EXT10
*4
*5
*6
Each Block
Register
decoder
*7
EXTII
Interrupt
Micro
Controller
controller
Timer
DRAM
Data bus[0.7]
Data bus[0.15]
Sub-code I/F
de-interleve
Adress generator
Sub-code ECC
Address generator
De-scramble &
Buffering
Address generator
ECC & EDC
Address generator
ATAPI I/F
Data output input I/F
Address generator
Microcontroller
RAM access
Address generator
*8
Gray Block si characteristic of LG895300.
LC895300
LC895299
Adress bus[0.18]
Each Block
Bus control
siganl
Bus
Arbiter
&
DRAM
controller
Buffer
DRAM
*13
XTALCK
Clock
generator
XTAL
Each Block
*9
*10
ZOE, ZWE, ZCE
128K
D0~D7
EEPROM
A0~A16
1.5K
RAM