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Detailed Control Output Signal Circuit
Control signals to be output include handshake output signals.
SN74LV125A
Figure 3.5. Control signal output circuit
What is the Control Signal?
External clock signal (EXTCLK0/EXTCLK1)
These signals input external pacer clocks. The maximum frequency is 10MHz.
When the external clock input is set as the clock source, pattern input or output occurs at the falling
edge of this signal.
EXTCLK0
EXTCLK1
tPWH
tPWH :
Clock pulse high width
tPWL :
Clock pulse low width
Figure 3.6. External clock signal
Eternal start signal (EXTSTART0/EXTSTART1)
These input signals start bus mastering with an external signal. The signal level is LVTTL and you
can select and enable the rising or falling edge with the software. In order to detect the signal edge, a
high- and low-level hold time of 50ns is needed at minimum.
EXTSTART0
EXTSTSRT1
tHIH
tHIH :
High level hold time
tHIL :
Low level hold time
Figure 3.7. External start signal
DIO-32DM-PE
Board
EXTACK0
EXTREQ1
Output pin
GND
tPWL
50ns (Min.)
50ns (Min.)
tHIL
tHIH
50ns (Min.)
50ns (Min.)
External circuit
5V TTL IC or LVTTL IC
3. External Connection
41
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