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Aaeon ICS-6270 User Manual

Din rail 6 lan ports industrial-grade network appliance
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ICS-6270
Industrial DIN Rail Network Appliance
nd
User's Manual 2
Ed

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Summary of Contents for Aaeon ICS-6270

  • Page 1 ICS-6270 Industrial DIN Rail Network Appliance User’s Manual 2...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel  Corporation Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity ICS-6270  DIN Rail Kit  SATA Cable  SATA Power Cable  Memory heatsink  Thermal Pad  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Preface...
  • Page 6 All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale. Do not use any cables or adapters not supplied by AAEON to prevent system malfunction or fires.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 – Product Specifications ..................14 Specifications ......................15 Chapter 2 – Hardware Information ..................18 Dimensions ......................19 Jumpers and Connectors ..................22 List of Jumpers ....................... 24 2.3.1 CMOS Setting Selection (CN1 ............25 2.3.2 Auto PWRBTN Selection (JP1) ............
  • Page 12 3.4.6.2 Serial Port 2 Configuration ............ 51 3.4.7 Serial Port Console Redirection ............52 3.4.7.1 Console Redirection Settings ..........53 3.4.7.2 Legacy Console Redirection Settings ........56 3.4.7.3 Serial Port for Out-of-Band Management/Windows Emergency Management Services(EMS) ............57 3.4.8 LAN Bypass Configuration ..............59 3.4.9 Digital IO Port Configuration .............
  • Page 13 C.2.2 Sample Code ..................100 Introduction to Software Reset Button Configuration ......... 102 C.3.1 Soft Reset Button Configuration ............. 103 C.3.2 Sample Code ..................104 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 – Product Specifications...

  • Page 15: Specifications

    Specifications System Intel Pentium N3350 processor SoC ® ® Processor  204-pin DDR3L 1867MHz SODIMM slot x 1, System Memory  up to 8GB Chipset  Intel® i211 (Co-lay with Intel® i210) Gigabit Ethernet  Ethernet x 6 Supports up to 2 pairs bypass function Bypass ...
  • Page 16 daughter board) USB 3.0 Port x 2 RJ-45 LAN ports with LEDs x 6 (ICS-6270A) VGA port x 1 GPIO Programmable Button x 1 Power LED x 1 Status LED x 1 HDD Active LED x 1 Bypass LED x 2 DIN Rail and Wall mount Rear Panel I/O ...
  • Page 17 Graphic Engine Intel® HD 505 Graphics  Output Interface  Environmental -40°C ~ 75°C (-40°F ~ 156°F) Operating Temperature  -40°C ~ 85°C (-40°F ~ 185°F) Storage Temperature  10 ~ 80% relative humidity, non-condensing Operating Humidity  10 ~ 80% @ 40°C, non-condensing Storage Humidity ...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions System Chapter 2 – Hardware Information...
  • Page 20 Board Component Side Chapter 2 – Hardware Information...
  • Page 21 Solder Side Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    Jumpers and Connectors Component Side Chapter 2 – Hardware Information...
  • Page 23 Solder Side Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application. Label Function Auto PWRBTN Selection CMOS Setting Selection Chapter 2 – Hardware Information...

  • Page 25: Cmos Setting Selection

    2.3.1 CMOS Setting Selection (CN1 1 2 3 1 2 3 Normal (Default)) Clear CMOS 2.3.2 Auto PWRBTN Selection (JP1) 1 2 3 1 2 3 Don’t use Auto PWRBTN Use Auto PWRBTN Chapter 2 – Hardware Information...

  • Page 26: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function DIMM1 DDR3L SODIMM SOCKET CPU_FAN1 4P SMART FAN KB/MS CN23 COM PORT CN13 SATA6G INTERFACE SATA POWER Mini Pci-E socket CN24 CFast CARD SOCKET...

  • Page 27: Digital I/O (Cn3)

    2.4.1 Digital I/O (CN3) This connector offers 4-pair of digital I/O functions and address is 801H. The pin definitions are illustrated below: Signal Signal Digital- IN/OUT1 Digital- IN/OUT2 Digital- IN/OUT3 Digital- IN/OUT4 Digital- IN/OUT5 Digital- IN/OUT6 Digital- IN/OUT7 Digital- IN/OUT8 2.4.2 DC-IN (CN1) Signal Signal...

  • Page 28: List Of Connectors For T461 Type A

    List of Connectors for T461 TYPE A Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function GIGA LAN GIGA LAN VGA PORT COM2/RS232/RS422/RS485 Chapter 2 – Hardware Information...

  • Page 29: Hard Disk Drive Installation

    Hard Disk Drive Installation Loosen the screw and remove the top case from the lower side. Chapter 2 – Hardware Information...
  • Page 30 Place the SATA Cable and the Power cable onto the motherboard.. Chapter 2 – Hardware Information...
  • Page 31 Put the SSD together and fasten them tightly with screws.. Chapter 2 – Hardware Information...
  • Page 32 Put the lid back on and fasten the screws securely. Chapter 2 – Hardware Information...

  • Page 33: Dimm Sink Installation

    DIMM Sink Installation Unscrew and remove the cover lid. Chapter 2 – Hardware Information...
  • Page 34 Place the DIMM onto the motherboard. Chapter 2 – Hardware Information...
  • Page 35 Glue the SINK onto the PAD. Chapter 2 – Hardware Information...
  • Page 36 Put the sink together and fasten them securely with screws. Chapter 2 – Hardware Information...
  • Page 37 . Put the lid back on and fasten the screws securely.. Chapter 2 – Hardware Information...

  • Page 38: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 – AMI BIOS Setup...

  • Page 39: System Test And Initialization

    4. The CMOS memory has lost power and the configuration information has been erased. The ICS-6270 CMOS memory has an integral lithium battery backup for data retention. You have to replace the battery when it finally runs down. Note: The Intel Apollo Lake platform only supports UEFI boot mode.

  • Page 40: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <Esc>...

  • Page 41: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 42: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 43: Advanced: Trusted Computing

    3.4.1 Advanced: Trusted Computing Options summary: Security Device Support Disabled Enabled Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Enabled Enable or Disable SHA-1 PCR Bank SHA256 PCR Bank Disabled...
  • Page 44 Storage Hierarchy Disabled Enabled Enable or Disable Storage Hierarchy Endorsement Hierarchy Disabled Enabled Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec Version TCG_1_2 TCG_2 Select the TCG2 Spec Version Support, TCG_1_2: the Compatible mode for Win8/Win10, TCG_2: Support new TCG2 protocol and event format for Win10 or later Physical Presence Spec Version Select to Tell O.S.

  • Page 45: Advanced: Cpu Configuration

    3.4.2 Advanced: CPU Configuration Options summary: Intel Virtualization Technology Disabled Enabled When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology VT-d Disabled Enabled Enable/Disable CPU VT-d EIST Disabled Enabled Enable/Disable Intel SpeedStep Power Limit 1 Enable Disabled Enabled Enable/Disable Power Limit 1...

  • Page 46: Advanced: Sata Drives

    3.4.3 Advanced: SATA Drives Options summary : Chipset SATA Disabled Enabled Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). Chapter 3 – AMI BIOS Setup...

  • Page 47: Advanced: Usb Configuration

    3.4.4 Advanced: USB Configuration Options summary : Legacy USB Support Disabled Enabled Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Chapter 3 – AMI BIOS Setup...

  • Page 48: Advanced: Hardware Monitor

    3.4.5 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 49: Advanced: Sio Configuration

    3.4.6 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 50: Serial Port 1 Configuration

    3.4.6.1 Serial Port 1 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts. Mode: RS232 RS422...

  • Page 51: Serial Port 2 Configuration

    3.4.6.2 Serial Port 2 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 52: Serial Port Console Redirection

    3.4.7 Serial Port Console Redirection Options summary: Console Redirection Disabled Enabled Console Redirection Enabled or Disabled. Chapter 3 – AMI BIOS Setup...

  • Page 53: Console Redirection Settings

    3.4.7.1 Console Redirection Settings Options summary: Terminal Type VT100 VT100+ VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits per second 9600 19200...
  • Page 54 Parity None Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1’s in the data bits is even. Odd: parity bit is 0 if num of 1’s in the data bits is odd.
  • Page 55 The Setting Specify if BootLoader is selected than Legacy console redirection is disabled before booting to Legacy OS. Default value is Always Enable which means Legacy console Redirection is enabled for Legacy OS. Chapter 3 – AMI BIOS Setup...

  • Page 56: Legacy Console Redirection Settings

    3.4.7.2 Legacy Console Redirection Settings Legacy Serial Redirection Port COM0 Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages Chapter 3 – AMI BIOS Setup...

  • Page 57: Serial Port For Out-Of-Band Management/Windows

    3.4.7.3 Serial Port for Out-of-Band Management/Windows Emergency Management Services(EMS) Options summary: Terminal Type VT100 VT100+ VT-UTF8 ANSI VT-UTF8 is the preferred terminal type for out-of-band management. The next best choice is VT100+ and then VT100. See above, in Console Redirection Settings page, for more Help with Terminal Type/Emulation.
  • Page 58 Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a ‘stop’ signal can be sent to stop the data flow. Once the buffers are empty, a ‘start’ signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.

  • Page 59: Lan Bypass Configuration

    3.4.8 LAN Bypass Configuration Options summary : STATUS LED CTRL LED OFF RED LED ON RED LED BLINK RED LED FAST BLINK GREEN LED ON GREEN LED BLINK GREEN LED FAST BLINK Configure LAN Bypass Status LED. LAN kit Power ON Bypass PassTru Setting LAN kit function behavior when power on.(Bypass/Pass Through)
  • Page 60 WDT configuration Force Bypass SystemReset Configure WDT behavior , System Reset Force Bypass Chapter 3 – AMI BIOS Setup...

  • Page 61: Digital Io Port Configuration

    3.4.9 Digital IO Port Configuration DIO_P#1~4 Input Output Set DIO as Input or Output DIO_P#5~8 Input Output Set DIO as Input or Output DIO_P#1~4 Direction High Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 62: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 63: Chipset: North Bridge

    3.5.1 Chipset: North Bridge Options summary: Primary Display PCIe Select which of IGD/PCI Graphics device should be Primary Display Chapter 3 – AMI BIOS Setup...

  • Page 64: North Bridge: Ami Graphic Output Protocol Policy

    3.5.1.1 North Bridge: AMI Graphic Output Protocol Policy Options summary : Output Select Output Interface Chapter 3 – AMI BIOS Setup...

  • Page 65: Setup Submenu: Security

    Setup submenu: Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.

  • Page 66: Setup Submenu: Boot

    Setup submenu: Boot Options summary : Quite Boot Disabled Enabled Enables or disables Quiet Boot option. Network Stack Disabled Enabled Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup...

  • Page 67: Setup Submenu: Exit

    Setup submenu: Exit Chapter 3 – AMI BIOS Setup...

  • Page 68: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 69: Driver Installation

    Driver Installation Please download the driver from AAEON website. It contains all the drivers and utilities you need to setup your product. Follow the steps below to install the drivers. Step 1 – Install Chipset Drivers Open the Step 1 - Chipset folder followed by the SetupChipset.exe file...
  • Page 70 Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Chapter 4 – Driver Installation...

  • Page 71: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A – Watchdog Timer Programming...

  • Page 72: Watchdog Timer Initial Program

    A.1 Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 73 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 74 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 75 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 76 ************************************************************************************ VOID SIOEnterMBPnPMode(){ Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...
  • Page 77 ************************************************************************************ VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 << BitNum); TmpValue |= (Value << BitNum); IOWriteByte(SIOData, TmpValue); SIOExitMBPnPMode(); VOID SIOByteSet(byte LDN, byte Register, byte Value){ SIOEnterMBPnPMode();...

  • Page 78: Appendix B - I/O Information

    Appendix B Appendix B – I/O Information...

  • Page 79: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 80 Appendix B – I/O Information...

  • Page 81: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 82: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 83 Appendix B – I/O Information...
  • Page 84 Appendix B – I/O Information...
  • Page 85 Appendix B – I/O Information...
  • Page 86 Appendix B – I/O Information...
  • Page 87 Appendix B – I/O Information...
  • Page 88 Appendix B – I/O Information...
  • Page 89 Appendix B – I/O Information...
  • Page 90 Appendix B – I/O Information...
  • Page 91 Appendix B – I/O Information...

  • Page 92: Appendix C - Standard Lan Bypass Platform Setting

    Appendix C Appendix C – Standard LAN Bypass Platform Setting...

  • Page 93: Introduction To Led

    Introduction to LED ICS-6270 provides a LED indicator which can change the LED status by AAEON SDK. User is able to program the LED status to express different status. Appendix C – Standard LAN Bypass Platform Setting...

  • Page 94: Status Led Configuration

    C.1.1 Status LED Configuration The LED status indicator of FWS-2273 is programmable with AAEON SDK for your application. Table 1 : Turth Table of Status LED STA_LED2 STA_LED2 STA_LED2 STA_LED2 LED Off Red Blinking (Slowly) Red Blinking (Quickly) Reserved Green Blinking (Slowly)

  • Page 95: Sample Code

    C.1.2 Sample Code ***************************************************************************************** ***** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ***************************************************************************************** ***** bData = aaeonSmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); switch( LED_FLAG) case 0: //LED Off //BIT2=0, BIT1=0, BIT0=0 bData = bData & 0xF8; break;...
  • Page 96 //Green LED On //BIT2=1, BIT1=1, BIT0=1 bData = (bData & 0xF8) | 0x07; break; case 5: //Green LED Blink //BIT2=1, BIT1=0, BIT0=1 bData = (bData & 0xF8) | 0x05; break; case 6: //Green LED Fast Blink //BIT2=1, BIT1=1, BIT0=0 bData = (bData & 0xF8) | 0x06; break;...

  • Page 97: Introduction To Lan Bypass

    Introduction to LAN Bypass ICS-6270 provides LAN Bypass kit and allow uninterrupted network traffic even if a single in-line appliance is shut down or hangs. Appendix C – Standard LAN Bypass Platform Setting...

  • Page 98: Lan Bypass

    C.2.1 LAN Bypass Table1: LAN Kit ID Select LAN_ID2 LAN_ID1 LAN_ID0 LAN kit selected LAN Kit 1 Selected LAN Kit 2 Selected Table2: LAN Bypass register table Function Description LAN_ID3 Use for selecting which LAN kit will be LAN_ID2 configured, refert to Table 1 of ID Select table of LAN kit.
  • Page 99 Table3: LAN Bypass register mapping table CPLD Slave Address 0x90 (Note1) Attribute Offset(SMBUS) BitNum Value LAN_ID3 0x01(Note2) (Table 1) LAN_ID2 0x01(Note2) (Table 1) LAN_ID1 0x01(Note2) (Table 1) LAN_ID0 0x01(Note2) (Table 1) PWR_ON 0x01(Note2) (Table 2) PWR_OFF 0x01(Note2) (Table 2) WDT_EN 0x01(Note2) (Table 2) ACT_EN...

  • Page 100: Sample Code

    C.2.2 Sample Code ***************************************************************************************** ***** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ***************************************************************************************** ***** // Select Lan Pair BYTE bLanSel = LAN_PAIR; BYTE bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); // Set Reg01h bit3 if(bLanSel &...
  • Page 101 bData = bData & 0xDF; else // Bypass bData = bData | 0x20; // WDT Action (Reg01h bit4) if(SET_WDT_RESET) // Reset bData = bData & 0xEF; else // Bypass bData = bData | 0x10; SmbusWriteByte(CPLD_SLAVE_ADDRESS, OFFSET, bData); // Apply Settings (Reg01h bit7) bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET);...

  • Page 102: Introduction To Software Reset Button Configuration

    Introduction to Software Reset Button Configuration ICS-6270 provides a general propose input button which status get by AAEON SDK. Appendix C – Standard LAN Bypass Platform Setting...

  • Page 103: Soft Reset Button Configuration

    C.3.1 Soft Reset Button Configuration Table 1 : Soft Reset Button register mapping table Attribute Register(I/O) BitNum Value Attribute BTN_STS 0xA05(Note1) 4(Note2) (Note3) BTN_STS Table 2 : LAN Bypass relative register table Function Description Reading this register returns the pin level status which is normal high active low.

  • Page 104: Sample Code

    C.3.2 Sample Code ************************************************************************************ #define Word BTN_STS //This parameter is represented from Note1 #define Byte BTN_STS_R //This parameter is represented from Note2 ************************************************************************************ Byte GET_Value (Word IoAddr, Byte BitNum,Byte Value){ BYTE TmpValue; TmpValue = inportb (IoAddr); return (TmpValue & (1 << BitNum)) ************************************************************************************ VOID Main(){ Byte RstBtn;...

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