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M
M EDIATEK
PRELIM INARY, SU BJECT TO CHANGE W ITH O U T NOTICE
BLOCK DIAGRAM
Control Signal (GPIO, ...)
A nalog Front End
CVBS (AV)
( x 3 ) i = >
ADC
S
^
ADC
Y P b P r— s
ADC
ADC
V G A (a R G B )
A nalog Path
Digital
Digital Path
< -
TTL
LVDS Tx
L V D S ^ —
M TK CONFIDENTIAL, NO D ISCLO SURE
3D TVD
Main Path
3D TVD
MDDi
HDTVD
PIP Pat
VG AD
= >
OSD
Merge
C olor
----- ^ -----
Gam m a
<
Dithering
MT8205
DS
MLC
PLC
DS
DI
à
2D Graph
OSD
US
ià
DSP
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