Table of Contents
Advertisement
Q022 : JS28F128P30T85
56-Lead TSOP Pinout (64/128/256-Mbit)
A 16
A15
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
VCC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
A24
RFU
VSS
Notes:
1.
A1 is the least significant address bit.
2.
A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
3.
A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
4.
Synchronous burst read operation is currently not supported for the TSOP package. The synchronous
read input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads.
1
2
3
4
5
6
7
8
9
10
11
Intel StrataFlash Æ
12
Embedded Memory (P 30)
13
14
56-Lead TSOP Pinout
15
14 mm x 20 mm
16
17
18
19
20
21
22
23
24
25
26
27
28
Top View
53
56
WAIT
55
A 17
54
DQ15
53
DQ7
52
DQ14
51
DQ6
50
DQ13
49
DQ5
48
DQ12
47
DQ4
46
ADV#
45
CLK
44
RST#
43
VPP
42
DQ11
41
DQ3
40
DQ10
39
DQ2
38
VCCQ
37
DQ9
36
DQ1
35
DQ8
34
DQ0
33
VCC
32
OE #
31
VSS
30
CE#
29
A 1
Hide quick links:
Advertisement
Table of Contents
