Aiwa CSD-FD73 HT Service Manual page 23

Pin No. Pin Name
38 LVSS
39 RVSS
40 RCHO
41 RVDD
42 MUTER
43 XVDD
44 XOUT
45 XIN
46 XVSS
47 SBSY
48 EFLG
49 PW
50 SFSY
51 SBCK
52 FSX
53 WRQ
54 RWC
55 SQOUT
56 COIN
57 CQCK
58 RES
59 T11
60 16M
61 4.2M
62 T5
63 CS
64 T1
I/O
– Left channel one-bit D/A converter ground. (Must be connected to 0V.)
- Right channel one-bit D/A converter ground. (Must be connected to 0V.)
O Right channel one-bit D/A converter output.
- Right channel one-bit D/A converter power supply.
O Right channel one-bit D/A converter mute output. (not used)
- Crystal oscillator power supply.
O
Connections for a 16.93 MHz crystal oscillator element.
I
- Crystal oscillator ground. (Must be connected to 0V.)
O Subcode clock synchronization signal output. (not used)
O C1, C2, sigle an double error correction monitor. (not used)
O Subcode P, Q, R, S, T, U and W output. (not used)
Subcode frame synchronization signal output. This signal falls when the subcode are
O
in standby state. (not used)
I Subcode readout clock input. This is a Schmitt input. (Must be connected to 0V.)
O Output pin for the 7.35 kHZ synchronization signal divided from the crystal oscillator. (Not used)
O Subcode Q output standby output.
I Read/write control input. This is a Schmitt input.
O Subcode Q output.
I Command input pin from control microprocessor.
Input for both the command input acquisition clock and the SQOUT pin subcode
I
readout clock input pin. This is Schmitt input.
I Reset input. This pin must be set low briefly after power is first applied.
O Test output. Leave open. (Normally output a low level). (Not used)
O 16.9344 MHz output. (Not used)
O 4.2336 MHz output.
I Test input. A pull-down resistor is built-in. (Must be connected to 0V.)
Chip seledt input. A pull-down resistor is built-in.
I
(Must be connected to 0V if not controlled.)
I Test input. No pull-down resistor. (Must be connected to 0V.)
Description
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