Philips EXP212 Service Manual page 11

TMS320DA150PGE160 – DIGITAL SIGNAL PROCESSOR DSP
Pin Name Direction
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1 CVSS1 GND
DSP ↔
2 A22
3 CVSS2 GND
4 DVDD1 +3.3V
DSP ↔
5 A10
CD10 →
6 HD7
DSP ↔
7 A11
DSP ↔
8 A12
DSP ↔
9 A13
DSP ↔
10 A14
DSP ↔
11 A15
12 CVDD1 +3.3V
→ DSP
13 HAS
14 DVSS1 GND
15 CVSS3 GND
16 CVDD2 +core
→ DSP
17 HCS
→ DSP
18 HR/W
→ DSP
19 READY
DSP → EPROM
20 PS
DSP →
21 DS
DSP →
22 IS
DSP → DRAM
23 R/W
DSP →
24 MSTRB
DSP →
25 IOSTRB
DSP →
26 MSC
DSP →
27 XF
DSP →
28 HOLDA
DSP →
29 IAQ
→ DSP
30 HOLD
→ DSP
31 BIO
→ DSP
32 MP/MC
33 DVDD2 +3.3V
34 CVSS4 GND
CD10 → DSP
35 BDR1
CD10 → DSP
36 BFSR1
37 CVSS5 GND
CD10 → DSP
38 BCLKR1
→ DSP
39 HCNTL0
40 DVSS2 GND
CD10 → DSP
41 BCLKR0
µP → DSP
42 BCLKR2
→ DSP
43 BFSR0
→ DSP
44 BFSR2
→ DSP
45 BDR0
→ DSP
46 HCNTL1
µP → DSP
47 BDR2
DSP → CD10
48 BCLKX0
µP → CD10
49 BCLKX2
50 CVSS6 GND
DSP →
51 HINT
52 CVDD3 +core
DSP → CD10
53 BFSX0
µP → DSP
54 BFSX2
DSP →
55 HRDY
56 DVDD3 +3.3V
57 DVSS3 GND
DSP ↔
58 HD0
DSP → CD10
59 BDX0
DSP → µP
60 BDX2
DSP →
61 IACK
→ DSP
62 HBIL
→ DSP
63 NMI
→ DSP
64 INT0
→ DSP
65 INT1
→ DSP
66 INT2
→ DSP
67 INT3
68 CVDD4 +core
DSP ↔
69 HD1
3-4
Description
ground for core CPU
parallel address bus
ground for core CPU
power supply for I/O pins
parallel address bus
reference current output pin
parallel address bus
parallel address bus
parallel address bus
parallel address bus
parallel address bus
power supply for core CPU
address strobe input
ground for I/O pins
ground for core CPU
power supply for core CPU
chip select input
read/write input
data ready input, indicates that an external device is prepared for a bus
transaction to be completed
program space select output, always high unless driven low for
communicating to a particular external space
data space select output, always high unless driven low for communicating
to a particular external space
I/O space select output, always high unless driven low for communicating to
a particular external space
read/write signal output, indicates transfer direction during communication to
an external device
memory strobe signal output
I/O strobe signal output
microstate complete output, indicates completion of all software wait states
external flag output, latched software programmable signal
Hold acknowledge, indicates that the processor is in a hold state
instruction acquisition signal output
hold input, asserted to request control of address, data and control lines
branch control input
microprocessor/microcomputer mode select
power supply for I/O pins
ground for core CPU
serial data receive input
frame synchronization pulse for receive input
ground for core CPU
serial shift clock
control input
ground for I/O pins
serial shift clock
serial shift clock
frame synchronization pulse for receive input
frame synchronization pulse for receive input
serial data receive input
control input
serial data receive input
transmit clock
transmit clock
ground for core CPU
interrupt output, used to interrupt the host
power supply for core CPU
frame synchronization pulse for transmit input/output
frame synchronization pulse for transmit input/output
ready output, informs the host when the HPI is ready for the next transfer
power supply for I/O pins
ground for I/O pins
parallel bidirectional data bus
serial data transmit output
serial data transmit output
interrupt acknowledge signal output
byte identification, identifies the first or second byte of transfer
nonmaskable interrupt input
external user interrupt input
external user interrupt input
external user interrupt input
external user interrupt input
power supply for core CPU
parallel bidirectional data bus