Dg-Board (4 Of 4) Block Diagram - Panasonic TH-42PZ77U Service Manual

TH-42PZ77U

15.16. DG-Board (4 of 4) Block Diagram

DG DIGITAL SIGNAL PROCESSOR
MICOM
HDMI INTERFACE
FULL HD
21
22
23
24
MVCLK-CLKIA
MVSYNC-VSIA
MHSYNC-HSIA
BOE2-GYIA3
BOE3-GYIA1
BOE4-GYIA4
BOE5-GYIA0
BOE6-GYIA7
BOE7-GYIA6
BOE8-GYIA2
BOE9-GYIA5
HQ1_XRST
FOR
FACTORY
DG4
USE
WP 2
SCL 4
SDA 5
TH-42PZ77U
DG-Board (4 of 4) Block Diagram
IC5001
IC5002
AVR 3.3V
SUB5V
DDR 2.5V
1 VDD VOUT 5
CE
FHD3.3V
5 VOUT
3
IC5012
VDDA_PLL_DDR AVDD_DDRCLK AVDD_DDR
AVR 3.3V
1 VDD VOUT 5 DAC_VDD
CE VDD_PLL2
3
FHQCKIN
VDD_PLL1
FHQVIN
VDDW
FHD1.2V
FHQHIN
PORT-THQ
VDD12
FHQYIN0-9
CLKIA
FHQCIN0-9
CLKIA
VSIA
VSIA
PORT-A
CLK0THQ1
HSIA
HSIA
(ADV)
THQVOUT
THQHOUT
RVIA0-7
GYIA0-7
THQYO0-9
GOE2-RVIA3 ROE2-RVIA1
BUIA0-7
GOE3-BUIA3 ROE3-BUIA1
THQCO0-9
GOE4-BUIA7 ROE4-BUIA0
GOE5-BUIA4 ROE5-RVIA2
X5000
GOE6-BUIA6 ROE6-BUIA2 XTALOUT
GOE7-RVIA7 ROE7-RVIA0
GOE8-RVIA5 ROE8-RVIA4 XTALIN
IC5100
GOE9-RVIA6 ROE9-BUIA5
GC5P_1st
FRCK02
NRST
PORT-E
OSDI0-7 PTVEN
CLK0E
(OUTPUT
OSDI8-15
VS0E
FOR PANEL)
HS0E
PORT-D
CLKID
(H264)
VSI BOE0-9
HSI GOE0-9
ROE0-9
TRST
VDD25
TCK
JTAG
TMS
TDI(TO_HQ1L) DQ0-DQ31
TDO
ADDRESS BUS
A0-A11
SCL0 SCL
SDA0 SDA
BA0,BA1
DQS0-DQS3
CONTROL BUS
SCL_MC
CKE,WE
RAS,CAS
SDA_MC
SDCLK0,NSDCL0
IC5000
64k EEPROM
FHD3.3V
7 8
WC VCC
6
SCL
5
SDA
TV_MAIN_ON
16 27 17
CTL CB1 CB2
30 OVP
18 OUT2-1
FHD9V
20 OUT2-2
G2 S2 G1 S1
19 LX2
D2 D2 D1 D1
TV_MAIN_ON
8 -INC2
Q5902
FHD1.2V
12 VO2
11 FB2
FHD3.3V
VDD 1
FPGA_XRST
CONFIG_DONE
PEAKS_OSDCK
PEAKS_OSDH
PEAKS_YS
PEAKS_YM
PEAKS_OSVO
PEAKS_OSHO
PEAKS_OSCKO
OSD_FLAG
PEAKS_OSD0-OSD15
FRCK_FPGA
IC5013
RESET
FHD3.3V
2 VDD OUT 4
DATA BUS
DQ0-DQ31
A0-A11
BA0,BA1
VDD
DQS0-DQS3
VDDQ
CKE,WE
RAS,CAS
CK,CK
IC5102
DDR-SDRAM
IC5006
AVR 2.5V
FHD3.3V
1 8
VOUT VDD
80
IC5901
DC-DC CONVERTER
SUB(FHD)9V
9V->1.2V,9V->3.3V
21
VB
VCC 23
OUT1-1 26
OUT1-2 24
G2 S2 G1 S1
LX1 25
D2 D2 D1 D1
-INC1 7
Q5901
VO1 3
FHD3.3V
FB1 4
IC5009 IC5008
AVR 2.5V AVR 1.5V
FHD3.3V
8 VIN VOUT 1 8 VIN VOUT 1
VDDI01 VDDI02 VDDI04
SCL0 SCL
SDA0 SDA VDDI03
VCCINT
VCCA_PLL1
VCCA_PLL2
NRST
CONF_DONE
PEAKS_OSDCK
PEAKS_OSDH
PEAKS_YS
PEAKS_YM
IC5105
PEAKS_OSVO
FPGA
PEAKS_OSHO
(CYCLONE) RE_E+
PEAKS_OSCKO
RE_E-
OSD_FLAG RD_E+
RD_E-
RC_E+
PEAKS
RC_E-
OSD0-15
RB_E+
RB_E-
RA_E+
FRCLKIN
27MHz RA_E-
RCLK E+
RCLK E-
NCFG
RCLK O+
PTVEN
RCLK O-
CLK0E
VS0E RE O+
HS0E
RE O-
RD O+
BOE0-9
RD O-
GOE0-9
RC O+
ROE0-9
RC O-
RB O+
RB O-
RA O+
RA O-
IC5010
FHD3.3V CONFIG ROM
3 VCC
DCLK 6 DCLK
ASDO 5 ASDI
DATAO 2 DATA
nCSO 1 NCS
TCK
CFG-JTAG
TMS
TDI
TDO
TH-42PZ77U
DG-Board (4 of 4) Block Diagram
DG5 TO D5
1 E+LVDS0
2 E-LVDS0
4 E+LVDS1
5 E-LVDS1
6 E+LVDS2
7 E-LVDS2
9 E+LVDS3
10 E-LVDS3
11 E+LVDS4
12 E-LVDS4
14 E+LVDSCLK
15 E-LVDSCLK
16 LVDS_DET
17 0+LVDSCLK
18 0-LVDSCLK
20 0+LVDS0
21 0-LVDS0
23 0+LVDS1
24 0-LVDS1
25 0+LVDS2
26 0-LVDS2
28 0+LVDS3
29 0-LVDS3
30 0+LVDS4
31 0-LVDS4