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Related Manuals for 4DSP AD484
Summary of Contents for 4DSP AD484
- Page 1 955 S Virginia Street, Suite 214, Reno, NV 89502, USA Email: support@4dsp.com This document is the property of 4DSP Inc. and may not be copied nor communicated to a third party without the written permission of 4DSP Inc. © 4DSP Inc. 2007...
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Page 2: Revision History
AD484 user manual V1.2 Revision History Date Revision Version 02-03-07 First release 03-29-07 Corrected typos 04-12-07 Added more details regarding clock synchronization AD484 User manual February 2007 www.4dsp.com - 2 -... -
Page 3: Table Of Contents
AD484 user manual V1.2 Table of Contents Acronyms and related documents ................4 Acronyms....................... 4 Related Documents ....................4 General description....................5 Installation ........................6 Requirements and handling instructions ..............6 Firmware and software................... 6 Design .......................... 6 FPGA devices ......................6 3.1.1... -
Page 4: Acronyms And Related Documents
AD484 user manual V1.2 1 Acronyms and related documents 1.1 Acronyms Analog to Digital Converter Digital to Analog Converter Digitally Controlled Impedance Double Data Rate Digital Signal Processing EPROM Erasable Programmable Read-Only Memory FBGA Fineline Ball Grid Array FPDP Front Panel Data Port... -
Page 5: General Description
The AD484 is a high performance PMC/XMC digitizer module dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements. The AD484 can interface to a PCI-express, PCI-X and/or PCI bus. In addition to four 125MSPS A/D channels, the AD484 offers fast on-board memory resources and two Virtex-4 FPGAs. -
Page 6: Installation
Drivers, API libraries and a program example working in combination with a pre-programmed firmware for both FPGAs are provided. The AD484 is delivered with an interface to the Xilinx PCI core in the Virtex-4 device A and an example VHDL design in the Virtex-4 device B so users can start digitizing and performing data manipulation right out of the box. - Page 7 X 64-bit 66MHz/133MHz, PCI 64-bit 66MHz and PCI 32-bit 33MHz are supported on the AD484. The bus type must be communicated at the time of the order so the right Virtex-4 device A firmware can be loaded into the flash prior to delivery.
- Page 8 AD484 user manual V1.2 3.1.1.6 Pn4 user I/O connector The Pn4 connector is wired to the Virtex-4 device A. The 32 lower bits are available only if an XC4VFX60 device is mounted on board. The 32 higher bits are available only if PCI 32-bit is used and only if specified at the time of order.
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Page 9: Virtex-4 Device B
AD484 user manual V1.2 3.1.2 Virtex-4 device B 3.1.2.1 Virtex-4 device B family and package The Virtex-4 device B is dedicated to interfacing to the A/D circuitry and can also perform Digital Signal Processing algorithms. It is available in the Virtex-4 SX or LX family devices and is packaged in a 1148-ball Fineline Ball Grid array. -
Page 10: Fpga Devices Configuration
FPGA configuration bitstream is stored in the flash for both FPGA devices, it will start reading programming the devices in SelecMap mode. Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector. - Page 11 AD484 user manual V1.2 Figure 4: switch (J1) location Default setting. The Virtex-4 device A configuration is loaded from the flash at power up. Virtex-4 device A safety configuration loaded from the flash at power up. To be used only if the Virtex-4 device A cannot be configured or does not perform properly with the switch in the OFF position.
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Page 12: Jtag
Figure 5: CPLD LED locations 3.2.3 JTAG A JTAG connector is available on the AD484 for configuration purposes. The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope. The JTAG connector is located on side 1 of the PCB in front (see Figure 6). -
Page 13: Clock Tree
V1.2 3.3 Clock tree The AD484 clock architecture offers an efficient distribution of low jitter clocks. In addition to the PCI Express bus, the MGT reference clocks of 106.25MHz and 125MHz (Epson EG2121CA) make it possible to implement several standards over the MGT I/Os connected to the optical transceivers. -
Page 14: A/D Inputs And Outputs Main Characteristics
14-bit Output Data Width 2’s Compliment or offset binary (Changeable via control Data Format register) 82dBs maximum (manufacturer) SFDR 70dBs maximum (manufacturer) Maximum Sampling Frequency 125MHz. Table 6: AD484 A/D characteristics AD484 User manual February 2007 www.4dsp.com - 14 -... -
Page 15: Analog Inputs
3.5.3 Multi-module Synchronization Several AD484 cards can be cascaded and still be synchronized since either the external reference or the external clock can be passed to the next module in the chain. The external reference goes through a 0-delay buffer and is then output via an SMA connector on the front panel. -
Page 16: Front Panel Optical Transceivers
V1.2 3.6 Front Panel optical transceivers Four 2.5Gb/s optical transceivers (LTP-ST11M) are available on the AD484 in the front panel area. They are connected to the MGT I/Os of the Virtex-4 device A. Infiniband protocols as well as Gigabit Ethernet and Fibre channel (sFPDP) can be implemented over the transceivers. -
Page 17: Power Requirements
AD484 user manual V1.2 4 Power requirements The power is supplied to the AD484 via the PMC and/or XMC connectors. Several DC-DC converters generate the appropriate voltage rails for the different devices and interfaces present on board. The AD484 power consumption depends mainly on the FPGA devices work load. By using high efficiency power converters, all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm. -
Page 18: External Power Connector For Stand Alone Mode
(AD484-SA). The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board. -
Page 19: System Side View
6.2 Convection cooling 600LFM minimum 6.3 Conduction cooling The AD484 can optionally be delivered as conduction cooled PMC. The AD484 is compliant to ANSI/VITA 20-2001 standard for conduction cooled PMC. 7 Safety This module presents no hazard to the user. -
Page 20: Emc
AD484 user manual V1.2 8 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system.
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