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WYSAAVDX7
Control No.
HD-AE-A100174
AC Specifications
Power-on timing / External sleep clock
Parameter
1
Valid Power / RESETn / Clock to PDn de-asserted
2 Input SLP_CLK frequency
3 Input SLP_CLK high voltage
4 Input SLP_CLK low voltage
5 Input SLP_CLK phase noise requirement
6 Input SLP_CLK slew rate limit (10-90%)
7 Input SLP_CLK duty cycle tolerance
<Power-on sequence>
PDn must remain asserted for minimum of Tpor after VBAT, VIO and SLP_CLK are stable.
RESETn must be inactive value (asserted high) when PDn is de-asserted (high level).
SLP_CLK
(32.768KHz)
External reset(RESETn), power down(PDn)
Parameter
1
RESETn pulse width
2
PDn pulse width
1. RESETn should be asserted while VBAT, VIO and SLP_CLK are stable and PDn is de-asserted (high level).
2. PDn should be asserted while VBAT, VIO and SLP_CLK are stable and RESETn is de-asserted (high level).
3. For lowest current consumption, apply all power rails to WYSAAVDX7 during the assertion of PDn pin.
(2/5)
Condition Symbol
VBAT
VIO
Tpor
PDn
Condition
TAIYO YUDEN
Control name
Electrical characteristics
Min
Tpor
300
Tf
V
0.8
IH
V
0.0
IL
PN
SR
DC
20
Tf
Symbol
Min
Trpw
1
Tppw
300
13-Nov.2013 Ver.0.9
TAIYO YUDEN
Typ
Max
Unit
ms
32.768
KHz
1.8
1.98
V
0.25
V
-125
dBc/Hz @100KHz
100
ns
80
%
Typ
Max
Unit
ms
ms
Tentative
Remark
Remark
Note1
Notes2, 3
9/16
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