A/D Interrupt; I 2 C Interrupt; Interrupt Priority - Holtek HT46R47 Handbook

nal interrupt occurs, the interrupt request flag, TF, T0F or T1F will be reset and the EMI bit will be
cleared to disable other interrupts.

A/D Interrupt

For an A/D interrupt to occur, the corresponding interrupt enable bit EADI must be first set. For the
HT46R47/HT46C47 devices, this is bit 3 of the INTC register, while for the HT46R22/HT46C22
and HT46R23/HT46C23 devices, this is bit 3 of the INTC0 register. For the HT46R24/HT46C24 de-
vices, this is bit 0 of the INTC1 register. An actual A/D interrupt will be initialized when the A/D con-
verter request flag ADF is set, a situation that will occur when an A/D conversion process has
completed. In the case of the HT46R47/HT46C47 devices, this is bit 6 of the INTC register, while
for the HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 6 of the INTC0 register.
For the HT46R24/HT46C24 devices, this is bit 4 of the INTC1 register. When the master interrupt
global enable bit is set, the stack is not full and the corresponding A/D interrupt enable bit is set, an
internal interrupt will be generated when the previously requested A/D conversion process fin-
ishes. With the exception of the HT46R24/HT46C24 devices, this will create a subroutine call to lo-
cation 0CH. For the HT46R24/HT46C24 devices, a subroutine call to location 10H will be created.
When an A/D interrupt occurs, the interrupt request flag ADF will be reset and the EMI bit will be
cleared to disable other interrupts.
2
I C Interrupt
2
For an I C interrupt to occur, the corresponding interrupt enable bit EHI must be first set. For the
HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 0 of the INTC1 register, while for
the HT46R24/HT46C24 devices, this is bit 1 of the INTC1 register. An actual I
2
tialized when the I C interrupt request flag HIF is set, a situation that will occur when a matching
2
I C slave address is received or from the completion of an I
HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 4 of the INTC1 register, while for
the HT46R24/HT46C24 devices, this is bit 5 of the INTC1 register. Note that as the
HT46R47/HT46C47 devices do not contain an I
2
has no associated I C enable bit or request flag. When the master interrupt global enable bit is set,
the stack is not full and the corresponding I
2
generated when a matching I C slave address is received or from the completion of an I
byte transfer. For the HT46R22/HT46C22 and HT46R23 HT46C23 devices, this will create a sub-
routine call to location 10H, while for the HT46R24/HT46C24 devices, a subroutine call to location
2
14H will be created. When an I C interrupt occurs, the interrupt request flag HIF will be reset and
the EMI bit will be cleared to disable other interrupts.

Interrupt Priority

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
Interrupt Source
External Interrupt
2
C data byte transfer. In the case of the
2
C interface, their interrupt control register INTC
2
C interrupt enable bit is set, an internal interrupt will be
HT46R47 HT46R22
HT46C47 HT46C22
Priority Priority
1 1
64
A/D Type MCU
2
C interrupt will be ini-
2
C data
HT46R23 HT46R24
HT46C23 HT46C24
Priority Priority
1 1