Xerox Dove Technical Reference Manual page 7

Dove lOP Board
3. lOP Memory and Interrupt Controllers
3.1 lOP Memory
3.l.1 Memory addressing
3.l.2 Memory mapping
3.2 Interrupts
3.2.1 Hardware
3.2.2. Theory of operations
3.2.2.1 Master interrupt controller
3.2.2.2 Slave interrupt controllers
3.2.3 Programmer interface
3.2.3.1 Reg~sters
3.2.3.2 Timing
4. Bus Arbiter and Mode Control
4.1 Hardware
4.2 Theory of Operations
4.2.1 Ethernet and rigid disk combinations
4.2.2 lOP, PCE, Ethernet, and rigid disk combinations
4.2.3 Arbiter flow diagrams
5. Rigid Disk Subsystem
Subsystem architecture
S~bsystem
programming overview
5.1 Rigid Disk Drive
5.l.1 Hardware
5.l.2 Theory/Programmer interface
5.2 Rigid Disk Controller
5.2.1 Hardware
5.2.2. Theory of operations
5.2.2.1 Command/status registers
5.2.2.2 Scratch pad and local memory
5.2.2.3 Drive status and drive control registers
5.2.2.4 Microcontroller data paths
5.2.2.5 Write logic data path
5.2.2.6 Read logic data path
5.2.2.7 Reading and writing the DMA and FIFO
ii
3-1
3-1
3-2
3-2
3-2
3-4
3-4
3-5
3-7
3-7
3-11
4-2
4-3
4-4
4-9
4-15
5-1
5-2
5-7
5-7
5-7
5-8
5-9
5-11
5-12
5-12
5-12
5-12
5-13
5-14
5-15
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