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Dove lOP Board
5.34
DMA command register
5-48
5.35
DMA status register
5-48
5.36
FIFO block diagram
5-51
5.37
Reset timing
5-54
5.38
Asynchronous read/write timing
5-54
5.39
Full flag from last write to first read
5-55
5.40
Empty flag from last read to first write
5-55
Section 6
6.1
Ethernet controller block diagram
6-2
6.2
Terminating resistor network for transceiver cable
6-4
6.3
Ethernet controller and interface pins and signals
6-5
Section 7
7.1
Floppy disk subsystem block diagram
7-1
7.2
Diskettes
7-2
7.3
8272 floppy disk controller pins and signals
7-4
7.4
8272 floppy disk controller interface pins and signals
7-5
7.5
9229 data separator pins and signals
7-7
7.6
System interface
7-8
7.7
FDC status register
7-11
7.8
lOP control register
7-14
7.9
Floppy disk format
7-17
Section 8
8.1
RS232C block diagram
8-1
8.2
8274 serial controller pins and signals
8-2
8.3
8254 timer pins and signals
8-5
8.4
RS232C system interface pins and signals
8-6
8.5
RS232C channel A DTE port
8-8
8.6
RS232C channel B DCE port
8-9
8.7
RS232C controller data paths
8-11
8.8
Timing for 8274 interrupt acknowledge
8-12
Section
9
9.1
8251A keyboard controller
9-1
9.2
8251A initialization
9-3
9.3
Command register during mode initialization
9-4
Table of Contents
ix
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