Sharp SM-SX100 Service Manual page 60

SM-SX100
IC807 VHiTDA1307/-1: 1-Bit Conversion (TDA1307) (2/2)
Pin No. Port Name Input/Output
39 CL Input (Note 2)
40 Vss
1
41 V
DD2
42 RAB Input (Note 2)
Notes
1. These pins are configured as internal pull-down.
2. These pins are configured as internal pull-up.
1fs AUDIO DATA INPUTS
WS
1
ERROR CONCELMENT,
INTERPOLATION, MUTING
DSR 12
DSL 11
DIGITAL SILENCE DETECTION
TEST1 36
TEST2 37
DA 38
CL 39
RAB 42
POR 20
V DD3 8
V DD1 21
V DDOSC 24
V DDAL 29
V DDAR 32
V DD2 41
27
DOL
BITSTREAM DATA OUTPUTS
Clock input, to be generated by the microprocessor
— Ground 1
— Supply voltage 2
Command/peak data request line
SCK SD EFAB
2 3
4
TDA1307
MULTIPLE FORMAT
INPUT INTERFACE
DIGITAL
OUTPUT
DEEMPHASIS FILTER
FIR HALFBAND FILTER
STAGE 1: 1fs to 2fs
DC-CANCELING FILTER
PEAK DETECTION
FADE FUNCTION
VOLUME CONTROL
FIR HALFBAND FILTER
STAGE 2: 2 fs to 4 fs
FIR HALFBAND FILTER
STAGE 3: 4 fs to 8 fs
DITHER AND SCALING
3rd/4th ORDER
NOISE SHAPER
28 35 34 33 26
NDOL CDAC NDOR DOR MODE
Figure 60 BLOCK DIAGRAM OF IC
Function
WS
19 RESYNC
SCK
10 DOBM
13 DSTB
EFAB
5 SBCL
6 SBDA
SBCL
SBDA
25 V SSOSC
CDEC
22 XTAL1
V DDC3
CRYSTAL
OSCIL-
V SSC2
23 XTAL2
LATOR
DOBM
DSL
15 CMIC
DSR
7 CDEC
DSTB
14 CLC1
CLC1
17 CLC2
CMIC
V SSC3
18 CDCC
9 V SS2
CLC2
16 V SS3
CDCC
30 V SSAL
31 V SSAR
RESYNC
40 V SS1
POR
V DDC1
– 60 –
1
42
2
41
SD 3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
TDA1307
11
32
12
31
13
30
14
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
RAB
V DDC2
V SSC1
CL
DA
TEST2
TEST1
CDAC
NDOR
DOR
V DDAR
V SSAR
V SSAL
V DDAL
NDOL
DOL
MODE
V SSOSC
V DDOSC
XTAL2
XTAL1