Eeproms 128K (16,384 X 8) 2-Wire Serial (Ic302) - VESTEL SAT 3600 Service Manual

SERVICE MANUAL
Bus Operations
The following operations can be performed using the appropriate bus cycles: Read(Array, Electronic Signature,
Block Protection Status), Write command, Output Disable, Standby, Reset, Block Protection, Unprotection,
Protection Verify, Unprotection Verify and Block Temporary Unprotection.
Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a
Command Interface (C.I.). For added data protection, program or erase execution starts after4 or 6 cycles. The first,
second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all
Program/Erase Controller instructions. The 'Command' itself and its confirmation, when applicable, are given on the
third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to
Read Array mode.
Instructions
Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block
Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C.
automatically handles all timing and verification of the Program and Erase operations. The Status Register Data
Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor
the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded
sequence to the Command Interface which is common to all instructions The third cycle inputs the instruction set-
up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for
Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase
require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data
to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded
sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in
order to read data from another block or to program data in another block, and then resumed. When power is first
applied or if V falls below V
CC

EEPROMs 128K (16,384 x 8) 2-wire Serial (IC302)

Features
•
Low-voltage and Standard-voltage Operation
– 5.0 (V = 4.5V to 5.5V)
CC
– 2.7 (V = 2.7V to 5.5V)
CC
– 1.8 (V = 1.8V to 3.6V)
CC
•
Internally Organized 16,384 x 8 and 32,768 x 8
•
2-wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
•
Write Protect Pin for Hardware and Software Data Protection
•
64-byte Page Write Mode (Partial Page Writes Allowed)
•
Self-timed Write Cycle (5 ms Typical)
•
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: > 4000V
•
Automotive Grade and Extended Temperature Devices Available
•
8-pin JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 14-lead TSSOP, and
8-pad Leadless Array Packages
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only
memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device's cascadable feature allows up to
four devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial
, the command interface is reset to Read Array.
LKO
Rev 1.0 21.10.02 16:23 Page 25