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Controller Board
The DSP TX modulation data is sent synchronously through the I2SCLK, I2SDAT,
ISFRM lines to the Exciter FPGA. The FPGA controls the clock and frame timing
of this interface, where DSP provides raw data. A 1pps signal from the DSP can be
provided for precise simulcast timing.
The DSP RX IF comes from the RX to DSP. The main RX1 and optional RX2 90
MHz IF signals are fed directly from the receivers to the DSP section RX sub board
through coax cables from CN2.
A.4.2.5 Fan Control
The PA fan interface has 4 pins. 12 V Power is switched with a pulse width FET.
Fan power noise spikes are attenuated by RFI network using L1 etc to eliminate
noise on 12 V power.
A speed control is provided for the fan. A pulse RPM sensor allows RPM to be
measured.
A.4.2.6 External Port and Serial Links
The Controller PCB has an external 10-pin port for diagnostic use with jumper
links JMP2 and JMP3 to select Debug access to MCU position A. Debug access to
Exciter position C.
The Controller can be talked to in position A of links JMP2 and JMP3 to its serial
port 2 and debug or loader program used. (To use the loader JMP1 must be taken
off)
The DSP I/F normally accesses controller serial port 1 but when DSP is not
connected this can also be selected using links JMP4 and JMP5 Position B.
(normally always A).
A.4.2.7 Auxiliary
The Controller PCB has 2 x 3.3 V linear regulators and a 5-V linear regulator.
It contains an interface for the 10 front panel LED indicators. (some future use)
These are for Power, Analog, RXA, RXB (diversity), Link (Ethernet on), P25
phase 1 (C4 FM), P25 phase 2, TX A (time slot A), TX B (time slot B).
The CPU A/D inputs monitor voltages for Supply in (48 V), RX VCO 2, RX VCO
1, TX VCO, Forward and Reflected voltages.
A-14
Appendix A - VHF Circuit Descriptions
ATLAS 4500 Multimode Station Technical Manual
May 2017
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