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3 7 63 1515 0
Pin No.
52
53
54
55
56
57
58
59
SEL_PLL1/TWS
60
SEL_PLL0/TSD
61
62
63
64
65
66
67
68
69
DOE#/MA9
70
71
72
73
74
75
TE
L 13942296513
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
www
99
100
101
.
102
103
104
http://www.xiaoyu163.com
Pin Name
I/O
LA17
O
Address bus for EPROM
LA18
O
Address bus for EPROM
LA19
—
Not used
TDMFS
I
Frame signal from CD DSP
TDMDR
I
Serial data from CD DSP
TDMCLK
I
Serial clock from CD DSP
TBCK
O
Bit clock for audio DAC
O
Audio strobe for audio DAC (TWS)
O
Serial data for audio DAC (TSD)
MCLK
O
Serial clock for audio DAC
CAS#
O
Column address strobe for DRAM
DRAS1#
—
Not used
VPP
—
Power supply (3.3V)
VSS
—
Ground
VCC
—
Power supply (2.6V)
DRAS0#
O
Row address strobe for DRAM
DWE#
O
Write enable for DRAM
O
Address bus for DRAM (MA9)
MA0
O
Address bus for DRAM
MA1
O
Address bus for DRAM
MA2
O
Address bus for DRAM
MA3
O
Address bus for DRAM
MA4
O
Address bus for DRAM
MA5
O
Address bus for DRAM
MA6
O
Address bus for DRAM
MA7
O
Address bus for DRAM
MA8
O
Address bus for DRAM
DBUS0
I/O
Data bus for DRAM
DBUS1
I/O
Data bus for DRAM
DBUS2
I/O
Data bus for DRAM
DBUS3
I/O
Data bus for DRAM
DBUS4
I/O
Data bus for DRAM
DBUS5
I/O
Data bus for DRAM
DBUS6
I/O
Data bus for DRAM
DBUS7
I/O
Data bus for DRAM
DBUS8
I/O
Data bus for DRAM
DBUS9
I/O
Data bus for DRAM
DBUS10
I/O
Data bus for DRAM
DBUS11
I/O
Data bus for DRAM
DBUS12
I/O
Data bus for DRAM
DBUS13
I/O
Data bus for DRAM
DBUS14
I/O
Data bus for DRAM
DBUS15
I/O
Data bus for DRAM
VCC
—
Power supply (2.6V)
RESET#
I
System reset
VSS
—
Ground
VSS_P
—
Ground
VCC_P
—
Power supply (2.6V)
x
ao
y
AUX20
O
Clock for SBSO
AUX21
I
SQSO data from CD DSP
i
AUX22
O
SQCK clock for CD DSP
AUX23
—
Pulled down to ground
AUX24
I
C2PO from CD DSP
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
Pin Description
1 5
0 5
8
2 9
9 4
m
co
CA-V100
9 9
2 8
9 9
21
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