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Logic Interface Characteristics
(1.8V ≤ V
≤ V
)
DD_IO
DD1,2
Symbol
Parameter
LOGIC INPUTS SS, SI, SCK, PWM_LED
V
Input Low Level
IL
V
Input High Level
IH
I
Logic Input Current
I
f
Clock Frequency
SCK
LOGIC INPUT NRST
V
Input Low Level
IL
V
Input High Level
IH
I
Logic Input Current
I
t
Reset Pulse Width
NRST
LOGIC OUTPUT SO
V
Output Low Level
OL
V
Output High Level
OH
SPI Interface
LP3931 is compatible with the SPI serial bus specification
and it operates as a slave. The transmission consists of
16-bit Write and Read Cycles. One cycle consists of 7 Ad-
dress bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit
high state defines a Write Cycle and low defines a Read
Cycle. SO output is normally in high-impedance state and it
is active only when Data is sent out during a Read Cycle. A
pull-up or pull-down resistor may be needed in SO line if a
Conditions
V
= 2.775V
DD_IO
I
= 3 mA
SO
I
= − 3 mA
SO
SPI Write Cycle
SPI Read Cycle
7
Min
Typ
V
− 0.5
DD_IO
−1.0
1.5
−1.0
10
0.3
V
− 0.5
V
DD_IO
DD_IO
floating logic signal can cause unintended current consump-
tion in the input where SO is connected. The Address and
Data are transmitted MSB first. The Slave Select signal SS
must be low during the Cycle transmission. SS resets the
interface when high and it has to be taken high between
successive Cycles. Data is clocked in on the rising edge of
the SCK clock signal, while data is clocked out on the falling
edge of SCK.
Max
Units
0.5
V
V
1.0
µA
13
MHz
0.5
V
V
1.0
µA
µs
0.5
V
− 0.3
V
20117307
20117308
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