Haier LET39C800HF Instruction Manual page 193

CN9 CN9
TO DVBS
24Pin 24Pin
1
GND
2 LNB_ON/OFF
LNB LNB_ON/OFF 2
TS1_D0
3
D0 TS1_D0 2
TS1_D3
4
D3 TS1_D3 2
5 TS1_D1
D1 TS1_D1 2
6 TS1_D2
D2 TS1_D2 2
TS1_D4
7
D4 TS1_D4 2
TS1_D5
8
D5 TS1_D5 2
9 TS1_D6
D6 TS1_D6 2
10 TS1_D7
D7 TS1_D7 2
11
GND
TS1_CK
12
CLK TS1_CK 2
13
GND
14 TS1_VLD
VLD TS1_VLD 2
15 TS1_START
START TS1_START 2
RESET_DMBT_S
16
RESET
T_SCL
17
SCL
18 T_SDA
SDA
19
5VA
5V
20 5VA
5V
21
GND
22
GND
23
12VA
12V
24
12VA
12V
25
GND
26
GND
VDD2.5
VDD2.5
MPEG_D5
MPEG_D4
R800 R800
If Sleep Mode function is required, control of 10K 10K
this pin will be from an external source. This
pin has a 10K pullup resistor internal to the
VDD1.2
package.
J6 = N/C (open), demod normal operating mode
J6 = logic 1, demod normal operating mode
J6 = Logic 0, demod in sleep mode
VDD2.5
R850 R850
LNB_ON/OFF
NC/0R-0402 NC/0R-0402
MPEG_D3
MPEG_D2
MPEG_D1
MPEG_D0
TO THE MPEG
DECODER
R818 1M R818 1M
Y800 Y800
FB800 FB800
30.4000 MHz 30.4000 MHz
C806 C806 10ppm
VDD1.2
33pF-NPO 33pF-NPO C807 C807 60Ÿ-0603 60Ÿ-0603
33pF-NPO 33pF-NPO
C808 C808
0.1uF(X7R) 0.1uF(X7R)
VDD1.2 VDD2.5
TS1_VLD 100R 100R R830 R830 MPEG_VALID 8GXX
TS1_START 100R 100R R834 R834 MPEG_SYNC R837 R837 R838 R838
TS1_CK 100R 100R R836 R836 MPEG_CLK 0R/8G75 0R/8G75
NC/0R NC/0R
D7 TS TS1_D7 100RX4 100RX4 RP48 RP48 MPEG_D7
TS1_D6 MPEG_D6
TS1_D5 MPEG_D5
TS1_D4 MPEG_D4
TS1_D2 100RX4 100RX4 RP49 RP49 MPEG_D2
TS1_D1 MPEG_D1
TS1_D3 MPEG_D3
TS1_D0 MPEG_D0
TS1_CK
TS1_D7
DVB-T
IF ANALOG INPUT
#IF_OUT
2010-07-01 #IF_OUT
C833 C833
22pF-NPO 22pF-NPO
IF_OUT
IF_OUT
VDD2.5 VDD1.2 VDD2.5 VDD1.2
VDD1.2
C800 C800 C801 C801
NC/0.1uF(X7R)/BOT NC/0.1uF(X7R)/BOT
A1 B12
RES SDAT
B2 C12
RES SCLT
C3 C11
RES DGND
B1 D12
RES VDD2.5
C2 D11
VDD2.5 RES
D3 E12
DGND RES
C1 D10
MPEG_D5 SDA
D2 E11
MPEG_D4 SCL
E3 F12
RES RESETN
D1 E10
RES AGC
E2 F11
RES RES
F3 D9
RES RES
E1 E8
VDD_1.2 DGND
F2 D8
DGND VDD2.5
G6 E9
CLKO RES
F1 U800 U800 D7
RES RES
G5 F10
CE_A2 DGND
H6 F9
RES VDD1.2
G4 E7
VDD2.5 RES
LGS-8G75/8G85-A1-BGA LGS-8G75/8G85-A1-BGA
H5 F8
DGND RES
J6 G12
BP1 RES
H4 F7
RES RES
J5 G11
Q9 DGND
G3 144 Pin BGA H12
Q8 VDD2.5
J4 G10
Q7 RES
G2 H11
Q6 RES
H3 J12
MPEG_D3 RES
G1 H10
MPEG_D2 RES
H2 J11
MPEG_D1 CE_A0
J3 K12
MPEG_D0 DGND
H1 J10
Q5 VDD1.2
J2 K11
Q4 VDD2.5
J1 L12
Q3 RES
K2 K10
Q2 GPIO0
K1 L11
XTALIN RES
L1 M12
XTALOUT RES
C810 C810
0.1uF(X7R) 0.1uF(X7R)
C811 C811
1n 1n
+ +
C809 C809
10uF(X7R) 10uF(X7R)
FB801 FB801
60Ÿ-0603 60Ÿ-0603 C813 C813
0.1uF(X7R) 0.1uF(X7R)
C814 C814
C812 C812 0.1uF 0.1uF
FB802 FB802
10uF(X7R) 10uF(X7R)
60Ÿ-0603 60Ÿ-0603 FB803 FB803
60Ÿ-0603 60Ÿ-0603 C820 C820 C821 C821
10uF(X7R) 10uF(X7R) 0.1uF(X7R) 0.1uF(X7R)
C822 C822
1n 1n
C832 C832
220pF 220pF
L800 L800
VDD2.5
0.82uH 0.82uH C835 C835
220pF 220pF
R840 R840 R841 R841
NC/20K NC/20K
NC/20K NC/20K
VBIAS
(nominally
R844 R844
1.5V)
NC/649R NC/649R
R845 R845 C846 C846
only 8G85 used. NC/1K NC/1K NC/0.1uF NC/0.1uF
FOR HK DTMB
VDD2.5
3.3VA
R804 R804
R802 R802 R803 R803 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K R805 R805 From Main
Q800 Q800
4.7K 4.7K
APM2322A APM2322A I2C Bus
TO TUNER
SDA_TU 2 3 T_SDA
T_SDA
SDA_TU 2
SCL_TU
SCL_TU 2
R807 R807
VDD2.5
0R-0402 0R-0402
Q801 Q801
8G75_SDA APM2322A APM2322A
8G75_SCL T_SCL
2 3
T_SCL
AGC
R809 R809 C802 C802
0R-0402 0R-0402 1uF 1uF
VDD2.5
VDD2.5
R812 R812
49.9K 1% 49.9K 1%
VDD1.2
Manual Reset
(Optional)
From reset circuit
active low
C803 C803
0.1uF 0.1uF
VDD2.5
R814 R814
R815 10K R815 10K NC/0R NC/0R
RESET_DMBT_S 2
w/ R15 = NU
2.5V
VDD1.2
I2C Address = 3A
VDD2.5 w/ R15 = 10K
I2C Address = 32
0V equal to or
greater than 500uS
R821 R821 R819 R819
0R/8G75 0R/8G75 0R/8G75 0R/8G75
R826 R826
150R 150R
R82510K R82510K
IF_AGC
IF_AGC 2
C804 C804 C805 C805
0.1uF 0.1uF 0.1uF 0.1uF
AGND
U801 U801
SY8008B SOT-23 SY8008B SOT-23
FB6 FB6
DMBT_5V 56Ÿ-1206 56Ÿ-1206
4
VIN LX
R851 R851 SY8008B SY8008B
EC803 EC803 + +
SOT-23 SOT-23
220uF/16V 220uF/16V 1K 1K
1
EN OUT/FB
C848 C848
100PF 100PF
DMBT_5V
Q802 Q802
AO3407 AO3407
5VA 2 3
C847 C847
0.1uF 0.1uF
R849 R849
ON
100K 100K
1E98 Bit B
R847 R847
OFF
1K 1K
1 Q803 Q803
LNB_ON/OFF
3904 3904
R846 R846
10K 10K
R846
VDD2.5
Bypassing for 8G75 / 8G85
R806 R806
4.7K 4.7K
VDD1.2
10uF Caps for VDD1.2 Power Plane to Dig GND
C816 C816 C817 C817
R808 R808 10uF(X7R) 10uF(X7R) NC/10uF(X7R)/BOT NC/10uF(X7R)/BOT
9.1K 9.1K
Cap placed at each VDD1.2 pin of U1 C823 0.1uF(X7R) C823 0.1uF(X7R)
C824 0.1uF(X7R) C824 0.1uF(X7R)
VDD1.2 900mA
C825 0.1uF(X7R) C825 0.1uF(X7R)
C831 0.1uF(X7R) C831 0.1uF(X7R)
C828 NC/0.1uF(X7R)/BOT C828 NC/0.1uF(X7R)/BOT
C829 NC/0.1uF(X7R)/BOT C829 NC/0.1uF(X7R)/BOT
C830 NC/0.1uF(X7R)/BOT C830 NC/0.1uF(X7R)/BOT
C827 NC/0.1uF(X7R)/BOT C827 NC/0.1uF(X7R)/BOT
C826 NC/0.1uF(X7R)/BOT C826 NC/0.1uF(X7R)/BOT
VDD2.5 100mA Cap at each VDD2.5 pin of U1
C837 0.1uF(X7R) C837 0.1uF(X7R)
C838 0.1uF(X7R) C838 0.1uF(X7R)
C839 0.1uF(X7R) C839 0.1uF(X7R)
C840 0.1uF(X7R) C840 0.1uF(X7R)
C841 0.1uF(X7R) C841 0.1uF(X7R)
C845 0.1uF(X7R) C845 0.1uF(X7R)
C843 0.1uF(X7R) C843 0.1uF(X7R)
C844 NC/0.1uF(X7R)/BOT C844 NC/0.1uF(X7R)/BOT
C842 NC/0.1uF(X7R)/BOT C842 NC/0.1uF(X7R)/BOT
L801 L801
10uH_1.5A 10uH_1.5A VDD1.2
C849 C849
R852 R852 30P 30P
10K 10K + + EC802 EC802
220uF/16V 220uF/16V
3
R853 R853
100K 100K
5
V =0.6X(1+R /R )
out up down
R854 R854
100K 100K
DMBT_5V
VDD2.5
U802 AMS1117-ADJ U802 AMS1117-ADJ
3 2
VIN VOUT
4
Vout
R839 R839
150R 150R
EC801 EC801
+ +
220uF/16V 220uF/16V
C836 C836
1uF 1uF R843 R843
150R 150R
V =1.25X(1+R /R )
out down up