Sony MDX-C8970 Service Manual page 50

Pin No. Pin Name
59 SCK
60 REDY
61 TRDT
62 XLAT
63 RVDT
64 XS24
65 VDD2
66 VSS3
67 to 69 SO1 to SO3
70 SOUT
71 SI1
72, 73 SI2, SI3
74 SIN
75 BCK
76 LRCK
77 XMST
78 VDD3
79 AVSP
80 XPLLEN
81 PLCLK
82 XECKSTP
83 AVDP
84 VSS4
85 to 94 T.P
95 VDD4
96 AVSD
97 to 99 T.P
100 AVDD
50
I/O
Serial data transfer clock signal input from the master controller (IC500) and liquid crystal display
I
drive controller (IC701)
Transfer enable signal output to the master controller (IC500)
O
"L": transfer prohibition
Serial data output to the master controller (IC500) and liquid crystal display drive controller
O
(IC701)
I
Serial data latch pulse input from the master controller (IC500)
I
Serial data input from the master controller (IC500)
Serial data 24/32 bit slot selection signal input terminal
I
"L": 24 bit slot, "H": 32 bit slot (validity at slave mode) (fixed at "H" in this set)
—
Power supply terminal (+3.3V) (digital system)
—
Ground terminal (digital system)
O
Serial data output terminal Not used (open)
O
Serial data output terminal Not used (open)
I
Serial data input from the CXD2652AR (IC301)
I
Serial data input terminal Not used (open)
I Serial data input terminal Not used (open)
I
Bit clock signal (2.8224 MHz) input from the CXD2652AR (IC301)
I
L/R sampling clock signal (44.1 kHz) input from the CXD2652AR (IC301)
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal input
I
from the master controller (IC500) "L": master mode, "H": slave mode
—
Power supply terminal (+3.3V) (digital system)
— Ground terminal (PLL system)
I
PLL enable signal input terminal Normally: fixed at "L"
O
PLL clock signal output terminal (22.5792 MHz)
PLL clock output control signal input from the master controller (IC500)
At "L" is input: fixed at "L" is PLCLK (pin *¡)
I
At "H" is input: PLL clock signal output from the PLCLK (pin *¡)
—
Power supply terminal (+3.3V) (PLL system)
—
Ground terminal (digital system)
I Input terminal for the test Normally: fixed at "L"
—
Power supply terminal (+3.3V) (digital system)
—
Ground terminal (for D-RAM)
I Input terminal for the test Normally: fixed at "L"
—
Power supply terminal (+3.3V) (for D-RAM)
Description